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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 136 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.384967451@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
294 lines
7 KiB
C
294 lines
7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* CS5536 PATA support
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* (C) 2007 Martin K. Petersen <mkp@mkp.net>
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* (C) 2009 Bartlomiej Zolnierkiewicz
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*
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* Documentation:
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* Available from AMD web site.
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*
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* The IDE timing registers for the CS5536 live in the Geode Machine
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* Specific Register file and not PCI config space. Most BIOSes
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* virtualize the PCI registers so the chip looks like a standard IDE
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* controller. Unfortunately not all implementations get this right.
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* In particular some have problems with unaligned accesses to the
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* virtualized PCI registers. This driver always does full dword
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* writes to work around the issue. Also, in case of a bad BIOS this
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* driver can be loaded with the "msr=1" parameter which forces using
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* the Machine Specific Registers to configure the device.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/msr.h>
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#define DRV_NAME "cs5536"
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enum {
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MSR_IDE_CFG = 0x51300010,
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PCI_IDE_CFG = 0x40,
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CFG = 0,
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DTC = 2,
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CAST = 3,
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ETC = 4,
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IDE_CFG_CHANEN = (1 << 1),
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IDE_CFG_CABLE = (1 << 17) | (1 << 16),
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IDE_D0_SHIFT = 24,
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IDE_D1_SHIFT = 16,
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IDE_DRV_MASK = 0xff,
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IDE_CAST_D0_SHIFT = 6,
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IDE_CAST_D1_SHIFT = 4,
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IDE_CAST_DRV_MASK = 0x3,
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IDE_CAST_CMD_SHIFT = 24,
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IDE_CAST_CMD_MASK = 0xff,
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IDE_ETC_UDMA_MASK = 0xc0,
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};
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static int use_msr;
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static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
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{
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if (unlikely(use_msr)) {
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u32 dummy;
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rdmsr(MSR_IDE_CFG + reg, *val, dummy);
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return 0;
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}
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return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
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}
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static int cs5536_write(struct pci_dev *pdev, int reg, int val)
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{
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if (unlikely(use_msr)) {
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wrmsr(MSR_IDE_CFG + reg, val, 0);
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return 0;
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}
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return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
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}
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static void cs5536_program_dtc(ide_drive_t *drive, u8 tim)
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{
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struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
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int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
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u32 dtc;
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cs5536_read(pdev, DTC, &dtc);
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dtc &= ~(IDE_DRV_MASK << dshift);
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dtc |= tim << dshift;
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cs5536_write(pdev, DTC, dtc);
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}
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/**
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* cs5536_cable_detect - detect cable type
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* @hwif: Port to detect on
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*
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* Perform cable detection for ATA66 capable cable.
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*
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* Returns a cable type.
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*/
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static u8 cs5536_cable_detect(ide_hwif_t *hwif)
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{
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struct pci_dev *pdev = to_pci_dev(hwif->dev);
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u32 cfg;
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cs5536_read(pdev, CFG, &cfg);
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if (cfg & IDE_CFG_CABLE)
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return ATA_CBL_PATA80;
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else
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return ATA_CBL_PATA40;
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}
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/**
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* cs5536_set_pio_mode - PIO timing setup
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* @hwif: ATA port
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* @drive: ATA device
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*/
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static void cs5536_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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static const u8 drv_timings[5] = {
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0x98, 0x55, 0x32, 0x21, 0x20,
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};
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static const u8 addr_timings[5] = {
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0x2, 0x1, 0x0, 0x0, 0x0,
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};
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static const u8 cmd_timings[5] = {
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0x99, 0x92, 0x90, 0x22, 0x20,
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};
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struct pci_dev *pdev = to_pci_dev(hwif->dev);
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ide_drive_t *pair = ide_get_pair_dev(drive);
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int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
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unsigned long timings = (unsigned long)ide_get_drivedata(drive);
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u32 cast;
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const u8 pio = drive->pio_mode - XFER_PIO_0;
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u8 cmd_pio = pio;
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if (pair)
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cmd_pio = min_t(u8, pio, pair->pio_mode - XFER_PIO_0);
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timings &= (IDE_DRV_MASK << 8);
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timings |= drv_timings[pio];
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ide_set_drivedata(drive, (void *)timings);
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cs5536_program_dtc(drive, drv_timings[pio]);
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cs5536_read(pdev, CAST, &cast);
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cast &= ~(IDE_CAST_DRV_MASK << cshift);
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cast |= addr_timings[pio] << cshift;
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cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT);
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cast |= cmd_timings[cmd_pio] << IDE_CAST_CMD_SHIFT;
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cs5536_write(pdev, CAST, cast);
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}
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/**
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* cs5536_set_dma_mode - DMA timing setup
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* @hwif: ATA port
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* @drive: ATA device
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*/
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static void cs5536_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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static const u8 udma_timings[6] = {
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0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
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};
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static const u8 mwdma_timings[3] = {
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0x67, 0x21, 0x20,
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};
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struct pci_dev *pdev = to_pci_dev(hwif->dev);
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int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
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unsigned long timings = (unsigned long)ide_get_drivedata(drive);
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u32 etc;
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const u8 mode = drive->dma_mode;
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cs5536_read(pdev, ETC, &etc);
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if (mode >= XFER_UDMA_0) {
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etc &= ~(IDE_DRV_MASK << dshift);
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etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
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} else { /* MWDMA */
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etc &= ~(IDE_ETC_UDMA_MASK << dshift);
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timings &= IDE_DRV_MASK;
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timings |= mwdma_timings[mode - XFER_MW_DMA_0] << 8;
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ide_set_drivedata(drive, (void *)timings);
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}
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cs5536_write(pdev, ETC, etc);
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}
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static void cs5536_dma_start(ide_drive_t *drive)
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{
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unsigned long timings = (unsigned long)ide_get_drivedata(drive);
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if (drive->current_speed < XFER_UDMA_0 &&
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(timings >> 8) != (timings & IDE_DRV_MASK))
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cs5536_program_dtc(drive, timings >> 8);
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ide_dma_start(drive);
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}
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static int cs5536_dma_end(ide_drive_t *drive)
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{
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int ret = ide_dma_end(drive);
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unsigned long timings = (unsigned long)ide_get_drivedata(drive);
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if (drive->current_speed < XFER_UDMA_0 &&
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(timings >> 8) != (timings & IDE_DRV_MASK))
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cs5536_program_dtc(drive, timings & IDE_DRV_MASK);
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return ret;
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}
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static const struct ide_port_ops cs5536_port_ops = {
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.set_pio_mode = cs5536_set_pio_mode,
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.set_dma_mode = cs5536_set_dma_mode,
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.cable_detect = cs5536_cable_detect,
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};
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static const struct ide_dma_ops cs5536_dma_ops = {
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.dma_host_set = ide_dma_host_set,
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.dma_setup = ide_dma_setup,
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.dma_start = cs5536_dma_start,
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.dma_end = cs5536_dma_end,
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.dma_test_irq = ide_dma_test_irq,
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.dma_lost_irq = ide_dma_lost_irq,
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.dma_timer_expiry = ide_dma_sff_timer_expiry,
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.dma_sff_read_status = ide_dma_sff_read_status,
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};
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static const struct ide_port_info cs5536_info = {
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.name = DRV_NAME,
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.port_ops = &cs5536_port_ops,
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.dma_ops = &cs5536_dma_ops,
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.host_flags = IDE_HFLAG_SINGLE,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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};
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/**
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* cs5536_init_one
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* @dev: PCI device
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* @id: Entry in match table
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*/
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static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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u32 cfg;
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if (use_msr)
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printk(KERN_INFO DRV_NAME ": Using MSR regs instead of PCI\n");
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cs5536_read(dev, CFG, &cfg);
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if ((cfg & IDE_CFG_CHANEN) == 0) {
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printk(KERN_ERR DRV_NAME ": disabled by BIOS\n");
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return -ENODEV;
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}
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return ide_pci_init_one(dev, &cs5536_info, NULL);
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}
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static const struct pci_device_id cs5536_pci_tbl[] = {
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
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{ },
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};
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static struct pci_driver cs5536_pci_driver = {
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.name = DRV_NAME,
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.id_table = cs5536_pci_tbl,
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.probe = cs5536_init_one,
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.remove = ide_pci_remove,
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.suspend = ide_pci_suspend,
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.resume = ide_pci_resume,
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};
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module_pci_driver(cs5536_pci_driver);
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MODULE_AUTHOR("Martin K. Petersen, Bartlomiej Zolnierkiewicz");
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MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, cs5536_pci_tbl);
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module_param_named(msr, use_msr, int, 0644);
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MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
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