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USB4 is the public specification based on Thunderbolt 3 protocol. There are some differences in register layouts and flows. In addition to PCIe and DP tunneling, USB4 supports tunneling of USB 3.x. USB4 is also backward compatible with Thunderbolt 3 (and older generations but the spec only talks about 3rd generation). USB4 compliant devices can be identified by checking USB4 version field in router configuration space. This patch adds initial support for USB4 compliant hosts and devices which enables following features provided by the existing functionality in the driver: - PCIe tunneling - Display Port tunneling - Host and device NVM firmware upgrade - P2P networking This brings the USB4 support to the same level that we already have for Thunderbolt 1, 2 and 3 devices. Note the spec talks about host and device "routers" but in the driver we still use term "switch" in most places. Both can be used interchangeably. Co-developed-by: Rajmohan Mani <rajmohan.mani@intel.com> Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20191217123345.31850-5-mika.westerberg@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Thunderbolt driver - NHI driver
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*
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* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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* Copyright (C) 2018, Intel Corporation
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*/
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#ifndef DSL3510_H_
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#define DSL3510_H_
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#include <linux/thunderbolt.h>
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enum nhi_fw_mode {
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NHI_FW_SAFE_MODE,
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NHI_FW_AUTH_MODE,
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NHI_FW_EP_MODE,
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NHI_FW_CM_MODE,
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};
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enum nhi_mailbox_cmd {
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NHI_MAILBOX_SAVE_DEVS = 0x05,
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NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
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NHI_MAILBOX_DRV_UNLOADS = 0x07,
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NHI_MAILBOX_DISCONNECT_PA = 0x10,
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NHI_MAILBOX_DISCONNECT_PB = 0x11,
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NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
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};
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int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
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enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
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/**
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* struct tb_nhi_ops - NHI specific optional operations
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* @init: NHI specific initialization
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* @suspend_noirq: NHI specific suspend_noirq hook
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* @resume_noirq: NHI specific resume_noirq hook
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* @runtime_suspend: NHI specific runtime_suspend hook
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* @runtime_resume: NHI specific runtime_resume hook
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* @shutdown: NHI specific shutdown
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*/
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struct tb_nhi_ops {
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int (*init)(struct tb_nhi *nhi);
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int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);
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int (*resume_noirq)(struct tb_nhi *nhi);
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int (*runtime_suspend)(struct tb_nhi *nhi);
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int (*runtime_resume)(struct tb_nhi *nhi);
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void (*shutdown)(struct tb_nhi *nhi);
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};
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extern const struct tb_nhi_ops icl_nhi_ops;
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/*
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* PCI IDs used in this driver from Win Ridge forward. There is no
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* need for the PCI quirk anymore as we will use ICM also on Apple
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* hardware.
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*/
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#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
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#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef
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#define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d
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#define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17
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#define PCI_CLASS_SERIAL_USB_USB4 0x0c0340
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#endif
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