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0d04eb4705
Package on-chip SRAM. It's always accessible from the ARM, so set up a standardized virtual address mapping into a 128 KiB area that's reserved for platform use. In some cases (dm6467) the physical addresses used for EDMA are not the same as the ones used by the ARM ... so record that info separately in the SOC data, for chips (unlike the OMAP-L137) where SRAM may be used with EDMA. Other blocks of SRAM, such as the ETB buffer or DSP L1/L2 RAM, may be unused/available on some system. They are ignored here. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
636 lines
15 KiB
C
636 lines
15 KiB
C
/*
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* TI DaVinci DM644x chip specific setup
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*
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* Author: Kevin Hilman, Deep Root Systems, LLC
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*
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* 2007 (c) Deep Root Systems, LLC. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/serial_8250.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <asm/mach/map.h>
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#include <mach/dm646x.h>
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#include <mach/clock.h>
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#include <mach/cputype.h>
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#include <mach/edma.h>
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#include <mach/irqs.h>
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#include <mach/psc.h>
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#include <mach/mux.h>
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#include <mach/time.h>
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#include <mach/serial.h>
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#include <mach/common.h>
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#include "clock.h"
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#include "mux.h"
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/*
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* Device specific clocks
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*/
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#define DM646X_REF_FREQ 27000000
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#define DM646X_AUX_FREQ 24000000
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static struct pll_data pll1_data = {
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.num = 1,
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.phys_base = DAVINCI_PLL1_BASE,
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};
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static struct pll_data pll2_data = {
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.num = 2,
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.phys_base = DAVINCI_PLL2_BASE,
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};
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static struct clk ref_clk = {
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.name = "ref_clk",
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.rate = DM646X_REF_FREQ,
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};
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static struct clk aux_clkin = {
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.name = "aux_clkin",
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.rate = DM646X_AUX_FREQ,
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};
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static struct clk pll1_clk = {
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.name = "pll1",
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.parent = &ref_clk,
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.pll_data = &pll1_data,
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.flags = CLK_PLL,
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};
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static struct clk pll1_sysclk1 = {
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.name = "pll1_sysclk1",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll1_sysclk2 = {
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.name = "pll1_sysclk2",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll1_sysclk3 = {
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.name = "pll1_sysclk3",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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};
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static struct clk pll1_sysclk4 = {
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.name = "pll1_sysclk4",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV4,
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};
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static struct clk pll1_sysclk5 = {
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.name = "pll1_sysclk5",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV5,
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};
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static struct clk pll1_sysclk6 = {
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.name = "pll1_sysclk6",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV6,
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};
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static struct clk pll1_sysclk8 = {
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.name = "pll1_sysclk8",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV8,
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};
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static struct clk pll1_sysclk9 = {
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.name = "pll1_sysclk9",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV9,
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};
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static struct clk pll1_sysclkbp = {
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.name = "pll1_sysclkbp",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV,
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};
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static struct clk pll1_aux_clk = {
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.name = "pll1_aux_clk",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll2_clk = {
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.name = "pll2_clk",
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.parent = &ref_clk,
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.pll_data = &pll2_data,
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.flags = CLK_PLL,
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};
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static struct clk pll2_sysclk1 = {
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.name = "pll2_sysclk1",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk dsp_clk = {
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.name = "dsp",
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.parent = &pll1_sysclk1,
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.lpsc = DM646X_LPSC_C64X_CPU,
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.flags = PSC_DSP,
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.usecount = 1, /* REVISIT how to disable? */
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};
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static struct clk arm_clk = {
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.name = "arm",
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.parent = &pll1_sysclk2,
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.lpsc = DM646X_LPSC_ARM,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk uart0_clk = {
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.name = "uart0",
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.parent = &aux_clkin,
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.lpsc = DM646X_LPSC_UART0,
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};
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static struct clk uart1_clk = {
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.name = "uart1",
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.parent = &aux_clkin,
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.lpsc = DM646X_LPSC_UART1,
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};
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static struct clk uart2_clk = {
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.name = "uart2",
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.parent = &aux_clkin,
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.lpsc = DM646X_LPSC_UART2,
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};
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static struct clk i2c_clk = {
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.name = "I2CCLK",
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.parent = &pll1_sysclk3,
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.lpsc = DM646X_LPSC_I2C,
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};
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static struct clk gpio_clk = {
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.name = "gpio",
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.parent = &pll1_sysclk3,
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.lpsc = DM646X_LPSC_GPIO,
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};
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static struct clk aemif_clk = {
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.name = "aemif",
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.parent = &pll1_sysclk3,
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.lpsc = DM646X_LPSC_AEMIF,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk emac_clk = {
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.name = "emac",
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.parent = &pll1_sysclk3,
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.lpsc = DM646X_LPSC_EMAC,
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};
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static struct clk pwm0_clk = {
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.name = "pwm0",
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.parent = &pll1_sysclk3,
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.lpsc = DM646X_LPSC_PWM0,
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.usecount = 1, /* REVIST: disabling hangs system */
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};
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static struct clk pwm1_clk = {
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.name = "pwm1",
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.parent = &pll1_sysclk3,
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.lpsc = DM646X_LPSC_PWM1,
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.usecount = 1, /* REVIST: disabling hangs system */
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};
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static struct clk timer0_clk = {
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.name = "timer0",
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.parent = &pll1_sysclk3,
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.lpsc = DM646X_LPSC_TIMER0,
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};
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static struct clk timer1_clk = {
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.name = "timer1",
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.parent = &pll1_sysclk3,
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.lpsc = DM646X_LPSC_TIMER1,
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};
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static struct clk timer2_clk = {
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.name = "timer2",
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.parent = &pll1_sysclk3,
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.flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
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};
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static struct clk vpif0_clk = {
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.name = "vpif0",
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.parent = &ref_clk,
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.lpsc = DM646X_LPSC_VPSSMSTR,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk vpif1_clk = {
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.name = "vpif1",
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.parent = &ref_clk,
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.lpsc = DM646X_LPSC_VPSSSLV,
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.flags = ALWAYS_ENABLED,
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};
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struct davinci_clk dm646x_clks[] = {
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "aux", &aux_clkin),
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CLK(NULL, "pll1", &pll1_clk),
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CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
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CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
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CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
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CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
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CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
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CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
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CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
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CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
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CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
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CLK(NULL, "pll1_aux", &pll1_aux_clk),
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CLK(NULL, "pll2", &pll2_clk),
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CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
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CLK(NULL, "dsp", &dsp_clk),
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CLK(NULL, "arm", &arm_clk),
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CLK(NULL, "uart0", &uart0_clk),
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CLK(NULL, "uart1", &uart1_clk),
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CLK(NULL, "uart2", &uart2_clk),
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CLK("i2c_davinci.1", NULL, &i2c_clk),
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CLK(NULL, "gpio", &gpio_clk),
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CLK(NULL, "aemif", &aemif_clk),
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CLK("davinci_emac.1", NULL, &emac_clk),
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CLK(NULL, "pwm0", &pwm0_clk),
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CLK(NULL, "pwm1", &pwm1_clk),
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CLK(NULL, "timer0", &timer0_clk),
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CLK(NULL, "timer1", &timer1_clk),
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CLK("watchdog", NULL, &timer2_clk),
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CLK(NULL, "vpif0", &vpif0_clk),
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CLK(NULL, "vpif1", &vpif1_clk),
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CLK(NULL, NULL, NULL),
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};
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static struct emac_platform_data dm646x_emac_pdata = {
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.ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
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.ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
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.ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
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.mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET,
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.ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
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.version = EMAC_VERSION_2,
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};
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static struct resource dm646x_emac_resources[] = {
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{
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.start = DM646X_EMAC_BASE,
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.end = DM646X_EMAC_BASE + 0x47ff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_DM646X_EMACRXTHINT,
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.end = IRQ_DM646X_EMACRXTHINT,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_DM646X_EMACRXINT,
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.end = IRQ_DM646X_EMACRXINT,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_DM646X_EMACTXINT,
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.end = IRQ_DM646X_EMACTXINT,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_DM646X_EMACMISCINT,
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.end = IRQ_DM646X_EMACMISCINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dm646x_emac_device = {
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.name = "davinci_emac",
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.id = 1,
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.dev = {
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.platform_data = &dm646x_emac_pdata,
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},
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.num_resources = ARRAY_SIZE(dm646x_emac_resources),
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.resource = dm646x_emac_resources,
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};
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#define PINMUX0 0x00
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#define PINMUX1 0x04
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/*
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* Device specific mux setup
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*
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* soc description mux mode mode mux dbg
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* reg offset mask mode
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*/
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static const struct mux_config dm646x_pins[] = {
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#ifdef CONFIG_DAVINCI_MUX
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MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
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MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
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MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
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MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
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MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
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MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
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MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
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MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
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MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
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MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
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MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
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MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
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MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
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MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
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#endif
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};
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static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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[IRQ_DM646X_VP_VERTINT0] = 7,
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[IRQ_DM646X_VP_VERTINT1] = 7,
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[IRQ_DM646X_VP_VERTINT2] = 7,
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[IRQ_DM646X_VP_VERTINT3] = 7,
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[IRQ_DM646X_VP_ERRINT] = 7,
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[IRQ_DM646X_RESERVED_1] = 7,
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[IRQ_DM646X_RESERVED_2] = 7,
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[IRQ_DM646X_WDINT] = 7,
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[IRQ_DM646X_CRGENINT0] = 7,
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[IRQ_DM646X_CRGENINT1] = 7,
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[IRQ_DM646X_TSIFINT0] = 7,
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[IRQ_DM646X_TSIFINT1] = 7,
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[IRQ_DM646X_VDCEINT] = 7,
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[IRQ_DM646X_USBINT] = 7,
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[IRQ_DM646X_USBDMAINT] = 7,
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[IRQ_DM646X_PCIINT] = 7,
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[IRQ_CCINT0] = 7, /* dma */
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[IRQ_CCERRINT] = 7, /* dma */
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[IRQ_TCERRINT0] = 7, /* dma */
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[IRQ_TCERRINT] = 7, /* dma */
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[IRQ_DM646X_TCERRINT2] = 7,
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[IRQ_DM646X_TCERRINT3] = 7,
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[IRQ_DM646X_IDE] = 7,
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[IRQ_DM646X_HPIINT] = 7,
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[IRQ_DM646X_EMACRXTHINT] = 7,
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[IRQ_DM646X_EMACRXINT] = 7,
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[IRQ_DM646X_EMACTXINT] = 7,
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[IRQ_DM646X_EMACMISCINT] = 7,
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[IRQ_DM646X_MCASP0TXINT] = 7,
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[IRQ_DM646X_MCASP0RXINT] = 7,
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[IRQ_AEMIFINT] = 7,
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[IRQ_DM646X_RESERVED_3] = 7,
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[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
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[IRQ_TINT0_TINT34] = 7, /* clocksource */
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[IRQ_TINT1_TINT12] = 7, /* DSP timer */
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[IRQ_TINT1_TINT34] = 7, /* system tick */
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[IRQ_PWMINT0] = 7,
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[IRQ_PWMINT1] = 7,
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[IRQ_DM646X_VLQINT] = 7,
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[IRQ_I2C] = 7,
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[IRQ_UARTINT0] = 7,
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[IRQ_UARTINT1] = 7,
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[IRQ_DM646X_UARTINT2] = 7,
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[IRQ_DM646X_SPINT0] = 7,
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[IRQ_DM646X_SPINT1] = 7,
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[IRQ_DM646X_DSP2ARMINT] = 7,
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[IRQ_DM646X_RESERVED_4] = 7,
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[IRQ_DM646X_PSCINT] = 7,
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[IRQ_DM646X_GPIO0] = 7,
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[IRQ_DM646X_GPIO1] = 7,
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[IRQ_DM646X_GPIO2] = 7,
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[IRQ_DM646X_GPIO3] = 7,
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[IRQ_DM646X_GPIO4] = 7,
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[IRQ_DM646X_GPIO5] = 7,
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[IRQ_DM646X_GPIO6] = 7,
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[IRQ_DM646X_GPIO7] = 7,
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[IRQ_DM646X_GPIOBNK0] = 7,
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[IRQ_DM646X_GPIOBNK1] = 7,
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[IRQ_DM646X_GPIOBNK2] = 7,
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[IRQ_DM646X_DDRINT] = 7,
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[IRQ_DM646X_AEMIFINT] = 7,
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[IRQ_COMMTX] = 7,
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[IRQ_COMMRX] = 7,
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[IRQ_EMUINT] = 7,
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};
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/*----------------------------------------------------------------------*/
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static const s8 dma_chan_dm646x_no_event[] = {
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0, 1, 2, 3, 13,
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14, 15, 24, 25, 26,
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27, 30, 31, 54, 55,
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56,
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-1
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};
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static struct edma_soc_info dm646x_edma_info = {
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.n_channel = 64,
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.n_region = 6, /* 0-1, 4-7 */
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.n_slot = 512,
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.n_tc = 4,
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.noevent = dma_chan_dm646x_no_event,
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};
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static struct resource edma_resources[] = {
|
|
{
|
|
.name = "edma_cc",
|
|
.start = 0x01c00000,
|
|
.end = 0x01c00000 + SZ_64K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "edma_tc0",
|
|
.start = 0x01c10000,
|
|
.end = 0x01c10000 + SZ_1K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "edma_tc1",
|
|
.start = 0x01c10400,
|
|
.end = 0x01c10400 + SZ_1K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "edma_tc2",
|
|
.start = 0x01c10800,
|
|
.end = 0x01c10800 + SZ_1K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "edma_tc3",
|
|
.start = 0x01c10c00,
|
|
.end = 0x01c10c00 + SZ_1K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = IRQ_CCINT0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = IRQ_CCERRINT,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
/* not using TC*_ERR */
|
|
};
|
|
|
|
static struct platform_device dm646x_edma_device = {
|
|
.name = "edma",
|
|
.id = -1,
|
|
.dev.platform_data = &dm646x_edma_info,
|
|
.num_resources = ARRAY_SIZE(edma_resources),
|
|
.resource = edma_resources,
|
|
};
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static struct map_desc dm646x_io_desc[] = {
|
|
{
|
|
.virtual = IO_VIRT,
|
|
.pfn = __phys_to_pfn(IO_PHYS),
|
|
.length = IO_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = SRAM_VIRT,
|
|
.pfn = __phys_to_pfn(0x00010000),
|
|
.length = SZ_32K,
|
|
/* MT_MEMORY_NONCACHED requires supersection alignment */
|
|
.type = MT_DEVICE,
|
|
},
|
|
};
|
|
|
|
/* Contents of JTAG ID register used to identify exact cpu type */
|
|
static struct davinci_id dm646x_ids[] = {
|
|
{
|
|
.variant = 0x0,
|
|
.part_no = 0xb770,
|
|
.manufacturer = 0x017,
|
|
.cpu_id = DAVINCI_CPU_ID_DM6467,
|
|
.name = "dm6467",
|
|
},
|
|
};
|
|
|
|
static void __iomem *dm646x_psc_bases[] = {
|
|
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
|
|
};
|
|
|
|
/*
|
|
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
|
|
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
|
|
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
|
|
* T1_TOP: Timer 1, top : <unused>
|
|
*/
|
|
struct davinci_timer_info dm646x_timer_info = {
|
|
.timers = davinci_timer_instance,
|
|
.clockevent_id = T0_BOT,
|
|
.clocksource_id = T0_TOP,
|
|
};
|
|
|
|
static struct plat_serial8250_port dm646x_serial_platform_data[] = {
|
|
{
|
|
.mapbase = DAVINCI_UART0_BASE,
|
|
.irq = IRQ_UARTINT0,
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM32,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.mapbase = DAVINCI_UART1_BASE,
|
|
.irq = IRQ_UARTINT1,
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM32,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.mapbase = DAVINCI_UART2_BASE,
|
|
.irq = IRQ_DM646X_UARTINT2,
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM32,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.flags = 0
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm646x_serial_device = {
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM,
|
|
.dev = {
|
|
.platform_data = dm646x_serial_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct davinci_soc_info davinci_soc_info_dm646x = {
|
|
.io_desc = dm646x_io_desc,
|
|
.io_desc_num = ARRAY_SIZE(dm646x_io_desc),
|
|
.jtag_id_base = IO_ADDRESS(0x01c40028),
|
|
.ids = dm646x_ids,
|
|
.ids_num = ARRAY_SIZE(dm646x_ids),
|
|
.cpu_clks = dm646x_clks,
|
|
.psc_bases = dm646x_psc_bases,
|
|
.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
|
|
.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
|
|
.pinmux_pins = dm646x_pins,
|
|
.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
|
|
.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
|
|
.intc_type = DAVINCI_INTC_TYPE_AINTC,
|
|
.intc_irq_prios = dm646x_default_priorities,
|
|
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
|
|
.timer_info = &dm646x_timer_info,
|
|
.wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
|
|
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
|
|
.gpio_num = 43, /* Only 33 usable */
|
|
.gpio_irq = IRQ_DM646X_GPIOBNK0,
|
|
.serial_dev = &dm646x_serial_device,
|
|
.emac_pdata = &dm646x_emac_pdata,
|
|
.sram_dma = 0x10010000,
|
|
.sram_len = SZ_32K,
|
|
};
|
|
|
|
void __init dm646x_init(void)
|
|
{
|
|
davinci_common_init(&davinci_soc_info_dm646x);
|
|
}
|
|
|
|
static int __init dm646x_init_devices(void)
|
|
{
|
|
if (!cpu_is_davinci_dm646x())
|
|
return 0;
|
|
|
|
platform_device_register(&dm646x_edma_device);
|
|
platform_device_register(&dm646x_emac_device);
|
|
return 0;
|
|
}
|
|
postcore_initcall(dm646x_init_devices);
|