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510d2358c4
Bus-speed could be default(12.5MHz) or defined by users in dts. Dw-i3c-master should not hard-code the initial speed to be I3C_BUS_TYP_I3C_SCL_RATE (12.5MHz) And because of Synopsys's I3C controller limit (hcnt/lcnt register length) and core-clk provided, there is a limit to bus speed, too. For example, when core-clk is 250 MHz, the bus speed cannot be lowered below 1MHz. Tested: tested with an i3c sensor and captured with a logic analyzer. Signed-off-by: Jack Chen <zenghuchen@google.com> Link: https://lore.kernel.org/r/20230216151057.293764-1-zenghuchen@google.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> |
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| .. | ||
| mipi-i3c-hci | ||
| dw-i3c-master.c | ||
| i3c-master-cdns.c | ||
| Kconfig | ||
| Makefile | ||
| svc-i3c-master.c | ||