Stephen Boyd 09d5dc586b PLL initialization for PLLs having both an integral and fractional mode ... (rk3036, rk3399) does now take into account the mode that the PLL is actually running at. As always also some additional and optimized PLL rates for rk3066 and rk3399, some additional clock ids for rk3066 and some additional clocks on rk3399 are now sucessfully handled inside their respective driver. -----BEGIN PGP SIGNATURE----- iQEtBAABCAAXBQJYJy9BEBxoZWlrb0BzbnRlY2guZGUACgkQ86Z5yZzRHYEZMwf/ XPnSVfSOSXSR3A6JOc7emX5vXVcXWq3xkt98l85qhiJO8yQg+vwFk2Ur7Q22cwJI ycg6K1EAokKt7/ZE48XZ0JYXQknxxSnO7ZU0MTVQVtQB7+oWr79VY+o+WylgsSZ7 LApU2lGniYXJOnQBTfNl8Zqyrg+M+q6zTW9HwK47TH51xjUiY9K+/nyNlAuEqBWQ TR8EuOQGxIQWHzJ7HFxCO4DNGEszrRkQMOcDsp2b5rxKTF3+waQne6OhX95JZpX5 PI12A1RC8+DNvYRZlhAnrmKHDycu6QYe18ZQADs5FPihMoxK4Eh/eXzZIIgXBkXd aOc4ljF03ry8mWyKtENVCg== =2Wr8 -----END PGP SIGNATURE----- Merge tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: PLL initialization for PLLs having both an integral and fractional mode (rk3036, rk3399) does now take into account the mode that the PLL is actually running at. As always also some additional and optimized PLL rates for rk3066 and rk3399, some additional clock ids for rk3066 and some additional clocks on rk3399 are now sucessfully handled inside their respective driver. * tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree clk: rockchip: add 400MHz to rk3066 clock rates table clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399 clk: rockchip: Use clock ids for cpu and peri clocks on rk3066 clk: rockchip: Add binding ids for cpu and peri clocks on rk3066 clk: rockchip: add 533.25MHz to rk3399 clock rates table		2016-11-14 18:38:35 -08:00
..
clk-cpu.c	clk: rockchip: fix cpuclk registration error handling	2016-05-30 09:40:23 +02:00
clk-ddr.c	clk: rockchip: don't return NULL when failing to register ddrclk branch	2016-10-16 02:39:58 +02:00
clk-inverter.c	clk: rockchip: don't return NULL when registering inverter fails	2016-02-15 23:35:20 +01:00
clk-mmc-phase.c	clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization"	2016-05-30 09:40:23 +02:00
clk-pll.c	clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused	2016-11-05 23:16:29 +01:00
clk-rk3036.c	clk: rockchip: release io resource when failing to init clk	2016-03-27 13:03:35 +02:00
clk-rk3188.c	clk: rockchip: add 400MHz to rk3066 clock rates table	2016-11-05 23:11:01 +01:00
clk-rk3228.c	clk: rockchip: export rk3228 MAC clocks	2016-07-01 01:50:11 +02:00
clk-rk3288.c	clk: rockchip: release io resource when failing to init clk	2016-03-27 13:03:35 +02:00
clk-rk3368.c	clk: rockchip: release io resource when failing to init clk	2016-03-27 13:03:35 +02:00
clk-rk3399.c	clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree	2016-11-05 23:12:55 +01:00
clk-rockchip.c	clk: rockchip: handle of_iomap failures in legacy clock driver	2016-08-23 18:00:25 +02:00
clk.c	clk: rockchip: add new clock-type for the ddrclk	2016-09-01 11:23:56 +02:00
clk.h	clk: rockchip: add new clock-type for the ddrclk	2016-09-01 11:23:56 +02:00
Makefile	clk: rockchip: add new clock-type for the ddrclk	2016-09-01 11:23:56 +02:00
softrst.c	clk: rockchip: Make reset_control_ops const	2016-03-29 16:29:46 -07:00