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6e74b12515
Since commit:
4d96f91091 ("x86/sev: Replace occurrences of sev_active() with cc_platform_has()")
... the SWIOTLB bounce buffer size adjustment and restricted virtio memory
setting also inadvertently apply to TDX: the code is using
cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT) as a gatekeeping condition,
which is also true for TDX, and this is also what we want.
To reflect this, move the corresponding code to generic mem_encrypt.c.
No functional changes intended.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Link: https://lore.kernel.org/r/20231010145220.3960055-2-alexander.shishkin@linux.intel.com
122 lines
3.2 KiB
C
122 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Memory Encryption Support Common Code
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*
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* Copyright (C) 2016 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*/
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#include <linux/dma-direct.h>
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#include <linux/dma-mapping.h>
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#include <linux/swiotlb.h>
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#include <linux/cc_platform.h>
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#include <linux/mem_encrypt.h>
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#include <linux/virtio_anchor.h>
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/* Override for DMA direct allocation check - ARCH_HAS_FORCE_DMA_UNENCRYPTED */
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bool force_dma_unencrypted(struct device *dev)
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{
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/*
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* For SEV, all DMA must be to unencrypted addresses.
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*/
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if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT))
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return true;
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/*
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* For SME, all DMA must be to unencrypted addresses if the
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* device does not support DMA to addresses that include the
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* encryption mask.
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*/
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if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) {
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u64 dma_enc_mask = DMA_BIT_MASK(__ffs64(sme_me_mask));
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u64 dma_dev_mask = min_not_zero(dev->coherent_dma_mask,
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dev->bus_dma_limit);
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if (dma_dev_mask <= dma_enc_mask)
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return true;
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}
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return false;
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}
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static void print_mem_encrypt_feature_info(void)
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{
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pr_info("Memory Encryption Features active:");
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if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
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pr_cont(" Intel TDX\n");
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return;
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}
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pr_cont(" AMD");
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/* Secure Memory Encryption */
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if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) {
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/*
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* SME is mutually exclusive with any of the SEV
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* features below.
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*/
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pr_cont(" SME\n");
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return;
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}
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/* Secure Encrypted Virtualization */
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if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT))
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pr_cont(" SEV");
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/* Encrypted Register State */
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if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT))
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pr_cont(" SEV-ES");
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/* Secure Nested Paging */
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if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
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pr_cont(" SEV-SNP");
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pr_cont("\n");
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}
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/* Architecture __weak replacement functions */
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void __init mem_encrypt_init(void)
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{
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if (!cc_platform_has(CC_ATTR_MEM_ENCRYPT))
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return;
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/* Call into SWIOTLB to update the SWIOTLB DMA buffers */
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swiotlb_update_mem_attributes();
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print_mem_encrypt_feature_info();
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}
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void __init mem_encrypt_setup_arch(void)
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{
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phys_addr_t total_mem = memblock_phys_mem_size();
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unsigned long size;
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if (!cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT))
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return;
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/*
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* For SEV and TDX, all DMA has to occur via shared/unencrypted pages.
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* Kernel uses SWIOTLB to make this happen without changing device
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* drivers. However, depending on the workload being run, the
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* default 64MB of SWIOTLB may not be enough and SWIOTLB may
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* run out of buffers for DMA, resulting in I/O errors and/or
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* performance degradation especially with high I/O workloads.
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*
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* Adjust the default size of SWIOTLB using a percentage of guest
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* memory for SWIOTLB buffers. Also, as the SWIOTLB bounce buffer
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* memory is allocated from low memory, ensure that the adjusted size
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* is within the limits of low available memory.
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*
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* The percentage of guest memory used here for SWIOTLB buffers
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* is more of an approximation of the static adjustment which
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* 64MB for <1G, and ~128M to 256M for 1G-to-4G, i.e., the 6%
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*/
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size = total_mem * 6 / 100;
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size = clamp_val(size, IO_TLB_DEFAULT_SIZE, SZ_1G);
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swiotlb_adjust_size(size);
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/* Set restricted memory access for virtio. */
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virtio_set_mem_acc_cb(virtio_require_restricted_mem_acc);
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}
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