273 lines
8.5 KiB
C
273 lines
8.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "reg_helper.h"
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#include "core_types.h"
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#include "link_encoder.h"
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#include "dcn31/dcn31_dio_link_encoder.h"
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#include "dcn35_dio_link_encoder.h"
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#define CTX \
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enc10->base.ctx
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#define DC_LOGGER \
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enc10->base.ctx->logger
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#define REG(reg)\
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(enc10->link_regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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enc10->link_shift->field_name, enc10->link_mask->field_name
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/*
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* @brief
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* Trigger Source Select
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* ASIC-dependent, actual values for register programming
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*/
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#define DCN35_DIG_FE_SOURCE_SELECT_INVALID 0x0
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#define DCN35_DIG_FE_SOURCE_SELECT_DIGA 0x1
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#define DCN35_DIG_FE_SOURCE_SELECT_DIGB 0x2
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#define DCN35_DIG_FE_SOURCE_SELECT_DIGC 0x4
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#define DCN35_DIG_FE_SOURCE_SELECT_DIGD 0x08
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#define DCN35_DIG_FE_SOURCE_SELECT_DIGE 0x10
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bool dcn35_is_dig_enabled(struct link_encoder *enc)
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{
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uint32_t enabled;
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struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
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REG_GET(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, &enabled);
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return (enabled == 1);
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}
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enum signal_type dcn35_get_dig_mode(
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struct link_encoder *enc)
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{
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uint32_t value;
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struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
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REG_GET(DIG_BE_CLK_CNTL, DIG_BE_MODE, &value);
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switch (value) {
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case 0:
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return SIGNAL_TYPE_DISPLAY_PORT;
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case 2:
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return SIGNAL_TYPE_DVI_SINGLE_LINK;
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case 3:
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return SIGNAL_TYPE_HDMI_TYPE_A;
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case 5:
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return SIGNAL_TYPE_DISPLAY_PORT_MST;
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default:
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return SIGNAL_TYPE_NONE;
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}
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return SIGNAL_TYPE_NONE;
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}
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void dcn35_link_encoder_setup(
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struct link_encoder *enc,
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enum signal_type signal)
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{
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struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
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switch (signal) {
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case SIGNAL_TYPE_EDP:
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case SIGNAL_TYPE_DISPLAY_PORT:
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/* DP SST */
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REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 0);
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break;
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case SIGNAL_TYPE_DVI_SINGLE_LINK:
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case SIGNAL_TYPE_DVI_DUAL_LINK:
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/* TMDS-DVI */
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REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 2);
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break;
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case SIGNAL_TYPE_HDMI_TYPE_A:
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/* TMDS-HDMI */
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REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 3);
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break;
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case SIGNAL_TYPE_DISPLAY_PORT_MST:
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/* DP MST */
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REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 5);
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break;
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default:
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ASSERT_CRITICAL(false);
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/* invalid mode ! */
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break;
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}
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REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, 1);
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}
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void dcn35_link_encoder_init(struct link_encoder *enc)
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{
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enc32_hw_init(enc);
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dcn35_link_encoder_set_fgcg(enc, enc->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dio);
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}
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void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enable)
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{
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struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
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REG_UPDATE(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, !enable);
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}
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static const struct link_encoder_funcs dcn35_link_enc_funcs = {
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.read_state = link_enc2_read_state,
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.validate_output_with_stream =
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dcn30_link_encoder_validate_output_with_stream,
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.hw_init = dcn35_link_encoder_init,
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.setup = dcn35_link_encoder_setup,
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.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
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.enable_dp_output = dcn31_link_encoder_enable_dp_output,
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.enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
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.disable_output = dcn31_link_encoder_disable_output,
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.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
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.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
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.update_mst_stream_allocation_table =
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dcn10_link_encoder_update_mst_stream_allocation_table,
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.psr_program_dp_dphy_fast_training =
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dcn10_psr_program_dp_dphy_fast_training,
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.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
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.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
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.enable_hpd = dcn10_link_encoder_enable_hpd,
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.disable_hpd = dcn10_link_encoder_disable_hpd,
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.is_dig_enabled = dcn35_is_dig_enabled,
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.destroy = dcn10_link_encoder_destroy,
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.fec_set_enable = enc2_fec_set_enable,
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.fec_set_ready = enc2_fec_set_ready,
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.fec_is_active = enc2_fec_is_active,
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.get_dig_frontend = dcn10_get_dig_frontend,
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.get_dig_mode = dcn35_get_dig_mode,
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.is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
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.get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
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.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
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};
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void dcn35_link_encoder_construct(
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struct dcn20_link_encoder *enc20,
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const struct encoder_init_data *init_data,
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const struct encoder_feature_support *enc_features,
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const struct dcn10_link_enc_registers *link_regs,
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const struct dcn10_link_enc_aux_registers *aux_regs,
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const struct dcn10_link_enc_hpd_registers *hpd_regs,
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const struct dcn10_link_enc_shift *link_shift,
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const struct dcn10_link_enc_mask *link_mask)
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{
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struct bp_connector_speed_cap_info bp_cap_info = {0};
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const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
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enum bp_result result = BP_RESULT_OK;
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struct dcn10_link_encoder *enc10 = &enc20->enc10;
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enc10->base.funcs = &dcn35_link_enc_funcs;
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enc10->base.ctx = init_data->ctx;
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enc10->base.id = init_data->encoder;
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enc10->base.hpd_source = init_data->hpd_source;
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enc10->base.connector = init_data->connector;
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if (enc10->base.connector.id == CONNECTOR_ID_USBC)
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enc10->base.features.flags.bits.DP_IS_USB_C = 1;
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enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
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enc10->base.features = *enc_features;
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enc10->base.transmitter = init_data->transmitter;
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/* set the flag to indicate whether driver poll the I2C data pin
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* while doing the DP sink detect
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*/
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/* if (dal_adapter_service_is_feature_supported(as,
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* FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
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* enc10->base.features.flags.bits.
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* DP_SINK_DETECT_POLL_DATA_PIN = true;
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*/
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enc10->base.output_signals =
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SIGNAL_TYPE_DVI_SINGLE_LINK |
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SIGNAL_TYPE_DVI_DUAL_LINK |
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SIGNAL_TYPE_LVDS |
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SIGNAL_TYPE_DISPLAY_PORT |
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SIGNAL_TYPE_DISPLAY_PORT_MST |
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SIGNAL_TYPE_EDP |
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SIGNAL_TYPE_HDMI_TYPE_A;
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enc10->link_regs = link_regs;
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enc10->aux_regs = aux_regs;
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enc10->hpd_regs = hpd_regs;
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enc10->link_shift = link_shift;
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enc10->link_mask = link_mask;
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switch (enc10->base.transmitter) {
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case TRANSMITTER_UNIPHY_A:
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enc10->base.preferred_engine = ENGINE_ID_DIGA;
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break;
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case TRANSMITTER_UNIPHY_B:
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enc10->base.preferred_engine = ENGINE_ID_DIGB;
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break;
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case TRANSMITTER_UNIPHY_C:
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enc10->base.preferred_engine = ENGINE_ID_DIGC;
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break;
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case TRANSMITTER_UNIPHY_D:
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enc10->base.preferred_engine = ENGINE_ID_DIGD;
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break;
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case TRANSMITTER_UNIPHY_E:
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enc10->base.preferred_engine = ENGINE_ID_DIGE;
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break;
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default:
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ASSERT_CRITICAL(false);
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enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
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}
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enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
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if (bp_funcs->get_connector_speed_cap_info)
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result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
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enc10->base.connector, &bp_cap_info);
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/* Override features with DCE-specific values */
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if (result == BP_RESULT_OK) {
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enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
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bp_cap_info.DP_HBR2_EN;
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enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
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bp_cap_info.DP_HBR3_EN;
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enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
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enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
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enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
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enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
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enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
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if (bp_cap_info.DP_IS_USB_C) {
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/*BIOS not switch to use CONNECTOR_ID_USBC = 24 yet*/
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enc10->base.features.flags.bits.DP_IS_USB_C = 1;
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}
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} else {
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DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
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__func__,
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result);
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}
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if (enc10->base.ctx->dc->debug.hdmi20_disable)
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enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
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}
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