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Linus Torvalds 825d150875 cxl for 5.12 
Introduce an initial driver for CXL 2.0 Type-3 Memory Devices. CXL is
 Compute Express Link which released the 2.0 specification in November.
 The Linux relevant changes in CXL 2.0 are support for an OS to
 dynamically assign address space to memory devices, support for
 switches, persistent memory, and hotplug. A Type-3 Memory Device is a
 PCI enumerated device presenting the CXL Memory Device Class Code and
 implementing the CXL.mem protocol. CXL.mem allows device to advertise
 CPU and I/O coherent memory to the system, i.e. typical "System RAM" and
 "Persistent Memory" in Linux /proc/iomem terms.
 
 In addition to the CXL.mem fast path there is an administrative command
 hardware mailbox interface for maintenance and provisioning. It is this
 command interface that is the focus of the initial driver. With this
 driver a CXL device that is mapped by the BIOS can be administered by
 Linux. Linux support for CXL PMEM and dynamic CXL address space
 management are to be implemented post v5.12.
 
 4cdadfd5e0 cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints
 Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
 
 8adaf747c9 cxl/mem: Find device capabilities
 Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
 
 b39cb1052a cxl/mem: Register CXL memX devices
 Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
 
 13237183c7 cxl/mem: Add a "RAW" send command
 Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
 
 472b1ce6e9 cxl/mem: Enable commands via CEL
 Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
 
 57ee605b97 cxl/mem: Add set of informational commands
 Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Merge tag 'cxl-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm

Pull initial support for CXL (Compute Express Link) from Dan Williams:
 "Introduce an initial driver for CXL 2.0 Type-3 Memory Devices.

  CXL is Compute Express Link which released the 2.0 specification in
  November. The Linux relevant changes in CXL 2.0 are support for an OS
  to dynamically assign address space to memory devices, support for
  switches, persistent memory, and hotplug.

  A Type-3 Memory Device is a PCI enumerated device presenting the CXL
  Memory Device Class Code and implementing the CXL.mem protocol.
  CXL.mem allows device to advertise CPU and I/O coherent memory to the
  system, i.e. typical "System RAM" and "Persistent Memory" in Linux
  /proc/iomem terms.

  In addition to the CXL.mem fast path there is an administrative
  command hardware mailbox interface for maintenance and provisioning.
  It is this command interface that is the focus of the initial driver.
  With this driver a CXL device that is mapped by the BIOS can be
  administered by Linux.

  Linux support for CXL PMEM and dynamic CXL address space management
  are to be implemented post v5.12"

Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
  4cdadfd5e0 ("cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints")
  13237183c7 ("cxl/mem: Add a "RAW" send command")
  472b1ce6e9 ("cxl/mem: Enable commands via CEL")
  57ee605b97 ("cxl/mem: Add set of informational commands")

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
  8adaf747c9 ("cxl/mem: Find device capabilities")
  b39cb1052a ("cxl/mem: Register CXL memX devices")

* tag 'cxl-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm:
  cxl/mem: Fix potential memory leak
  cxl/mem: Return -EFAULT if copy_to_user() fails
  MAINTAINERS: Add maintainers of the CXL driver
  cxl/mem: Add set of informational commands
  cxl/mem: Enable commands via CEL
  cxl/mem: Add a "RAW" send command
  cxl/mem: Add basic IOCTL interface
  cxl/mem: Register CXL memX devices
  cxl/mem: Find device capabilities
  cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints
2021-02-24 09:38:36 -08:00

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- '__rq_for_each_bio'
- 'rq_for_each_bvec'
- 'rq_for_each_segment'
- 'scsi_for_each_prot_sg'
- 'scsi_for_each_sg'
- 'sctp_for_each_hentry'
- 'sctp_skb_for_each'
- 'shdma_for_each_chan'
- '__shost_for_each_device'
- 'shost_for_each_device'
- 'sk_for_each'
- 'sk_for_each_bound'
- 'sk_for_each_entry_offset_rcu'
- 'sk_for_each_from'
- 'sk_for_each_rcu'
- 'sk_for_each_safe'
- 'sk_nulls_for_each'
- 'sk_nulls_for_each_from'
- 'sk_nulls_for_each_rcu'
- 'snd_array_for_each'
- 'snd_pcm_group_for_each_entry'
- 'snd_soc_dapm_widget_for_each_path'
- 'snd_soc_dapm_widget_for_each_path_safe'
- 'snd_soc_dapm_widget_for_each_sink_path'
- 'snd_soc_dapm_widget_for_each_source_path'
- 'tb_property_for_each'
- 'tcf_exts_for_each_action'
- 'udp_portaddr_for_each_entry'
- 'udp_portaddr_for_each_entry_rcu'
- 'usb_hub_for_each_child'
- 'v4l2_device_for_each_subdev'
- 'v4l2_m2m_for_each_dst_buf'
- 'v4l2_m2m_for_each_dst_buf_safe'
- 'v4l2_m2m_for_each_src_buf'
- 'v4l2_m2m_for_each_src_buf_safe'
- 'virtio_device_for_each_vq'
- 'while_for_each_ftrace_op'
- 'xa_for_each'
- 'xa_for_each_marked'
- 'xa_for_each_range'
- 'xa_for_each_start'
- 'xas_for_each'
- 'xas_for_each_conflict'
- 'xas_for_each_marked'
- 'xbc_array_for_each_value'
- 'xbc_for_each_key_value'
- 'xbc_node_for_each_array_value'
- 'xbc_node_for_each_child'
- 'xbc_node_for_each_key_value'
- 'zorro_for_each_dev'
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...
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