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Some hypervisors can allow the guest to use the Extended Destination ID field in the MSI address to address up to 32768 CPUs. This applies to all downstream devices which generate MSI cycles, including HPET, I/O-APIC and PCI MSI. HPET and PCI MSI use the same __irq_msi_compose_msg() function, while I/O-APIC generates its own and had support for the extended bits added in a previous commit. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20201024213535.443185-33-dwmw2@infradead.org
62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_MSI_H
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#define _ASM_X86_MSI_H
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#include <asm/hw_irq.h>
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#include <asm/irqdomain.h>
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typedef struct irq_alloc_info msi_alloc_info_t;
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int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
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msi_alloc_info_t *arg);
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/* Structs and defines for the X86 specific MSI message format */
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typedef struct x86_msi_data {
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u32 vector : 8,
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delivery_mode : 3,
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dest_mode_logical : 1,
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reserved : 2,
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active_low : 1,
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is_level : 1;
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u32 dmar_subhandle;
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} __attribute__ ((packed)) arch_msi_msg_data_t;
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#define arch_msi_msg_data x86_msi_data
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typedef struct x86_msi_addr_lo {
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union {
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struct {
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u32 reserved_0 : 2,
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dest_mode_logical : 1,
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redirect_hint : 1,
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reserved_1 : 1,
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virt_destid_8_14 : 7,
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destid_0_7 : 8,
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base_address : 12;
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};
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struct {
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u32 dmar_reserved_0 : 2,
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dmar_index_15 : 1,
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dmar_subhandle_valid : 1,
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dmar_format : 1,
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dmar_index_0_14 : 15,
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dmar_base_address : 12;
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};
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};
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} __attribute__ ((packed)) arch_msi_msg_addr_lo_t;
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#define arch_msi_msg_addr_lo x86_msi_addr_lo
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#define X86_MSI_BASE_ADDRESS_LOW (0xfee00000 >> 20)
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typedef struct x86_msi_addr_hi {
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u32 reserved : 8,
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destid_8_31 : 24;
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} __attribute__ ((packed)) arch_msi_msg_addr_hi_t;
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#define arch_msi_msg_addr_hi x86_msi_addr_hi
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#define X86_MSI_BASE_ADDRESS_HIGH (0)
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struct msi_msg;
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u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid);
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#endif /* _ASM_X86_MSI_H */
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