linux-stable/arch/mips/ralink
Stefan Roese 0b15394475
MIPS: ralink: Select CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8
Testing has shown, that when using mainline U-Boot on MT7688 based
boards, the system may hang or crash while mounting the root-fs. The
main issue here is that mainline U-Boot configures EBase to a value
near the end of system memory. And with CONFIG_CPU_MIPSR2_IRQ_VI
disabled, trap_init() will not allocate a new area to place the
exception handler. The original value will be used and the handler
will be copied to this location, which might already be used by some
userspace application.

The MT7688 supports VI - its config3 register is 0x00002420, so VInt
(Bit 5) is set. But without setting CONFIG_CPU_MIPSR2_IRQ_VI this
bit will not be evaluated to result in "cpu_has_vi" being set. This
patch now selects CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8 which results
trap_init() to allocate some memory for the exception handler.

Please note that this issue was not seen with the Mediatek U-Boot
version, as it does not touch EBase (stays at default of 0x8000.0000).
This is strictly also not correct as the kernel (_text) resides
here.

Signed-off-by: Stefan Roese <sr@denx.de>
[paul.burton@mips.com: s/beeing/being/]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
2018-12-23 08:04:15 -08:00
..
bootrom.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
cevt-rt3352.c MIPS: Convert to using %pOFn instead of device_node.name 2018-08-28 09:53:24 -07:00
clk.c MIPS: ralink: allow NULL clock for clk_get_rate 2017-09-06 12:37:45 +02:00
common.h MIPS: Change my email address 2016-05-13 14:02:18 +02:00
early_printk.c mips: unify prom_putchar() declarations 2018-07-17 09:40:17 -07:00
ill_acc.c MIPS: Convert to using %pOFn instead of device_node.name 2018-08-28 09:53:24 -07:00
irq-gic.c irqchip: mips-gic: Move gic_get_c0_*_int() to asm/mips-gic.h 2017-09-04 13:53:14 +02:00
irq.c MIPS: ralink: Fix request_mem_region error handling 2017-01-25 02:51:10 +01:00
Kconfig MIPS: ralink: Select CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8 2018-12-23 08:04:15 -08:00
Makefile MIPS: Change my email address 2016-05-13 14:02:18 +02:00
mt7620.c MIPS: ralink: Fix typo in mt7628 pinmux function 2017-11-13 11:46:37 +00:00
mt7621.c MIPS: ralink: Fix booting on MT7621 2018-03-22 00:06:30 +00:00
of.c mm: remove include/linux/bootmem.h 2018-10-31 08:54:16 -07:00
Platform MIPS: ralink: add MT7621 support 2016-01-20 00:39:20 +01:00
prom.c MIPS: ralink: Cosmetic change to prom_init(). 2017-01-03 16:34:48 +01:00
reset.c MIPS: ralink: Remove ralink_halt() 2018-03-21 23:43:39 +00:00
rt288x.c MIPS: Audit and remove any unnecessary uses of module.h 2017-02-14 09:00:25 +00:00
rt305x.c MIPS: ralink: Add rt3352 SPI_CS1 pinmux 2018-08-30 13:25:00 -07:00
rt3883.c MIPS: ralink: Fix typos in rt3883 pinctrl 2017-03-08 11:29:48 +01:00
timer-gic.c clocksource/drivers: Rename clocksource_probe to timer_probe 2017-06-14 11:59:16 +02:00
timer.c MIPS: ralink: Fix platform_get_irq's error checking 2018-01-10 16:45:44 +01:00