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efc91ae43c
Add driver code for the SiFive FU740 PRCI IP block. This IP block handles reset and clock control for the SiFive FU740 device and implements SoC-level clock tree controls and dividers. The link of unmatched as follow, and the U740-C000 manual would be present in the same page as soon. https://www.sifive.com/boards/hifive-unmatched This driver contains bug fixes and contributions from Henry Styles <hes@sifive.com> Erik Danie <erik.danie@sifive.com> Pragnesh Patel <pragnesh.patel@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Cc: Henry Styles <hes@sifive.com> Cc: Erik Danie <erik.danie@sifive.com> Cc: Pragnesh Patel <pragnesh.patel@sifive.com> Link: https://lore.kernel.org/r/20201209094916.17383-4-zong.li@sifive.com [sboyd@kernel.org: Include header to silence sparse] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
23 lines
635 B
C
23 lines
635 B
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (C) 2019 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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* Zong Li
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*/
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#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
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#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
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/* Clock indexes for use by Device Tree data and the PRCI driver */
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#define PRCI_CLK_COREPLL 0
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#define PRCI_CLK_DDRPLL 1
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#define PRCI_CLK_GEMGXLPLL 2
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#define PRCI_CLK_DVFSCOREPLL 3
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#define PRCI_CLK_HFPCLKPLL 4
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#define PRCI_CLK_CLTXPLL 5
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#define PRCI_CLK_TLCLK 6
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#define PRCI_CLK_PCLK 7
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#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
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