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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
116 lines
3.3 KiB
C
116 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Altera TSE SGDMA and MSGDMA Linux driver
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* Copyright (C) 2014 Altera Corporation. All rights reserved
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*/
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#ifndef __ALTERA_SGDMAHW_H__
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#define __ALTERA_SGDMAHW_H__
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/* SGDMA descriptor structure */
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struct sgdma_descrip {
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u32 raddr; /* address of data to be read */
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u32 pad1;
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u32 waddr;
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u32 pad2;
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u32 next;
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u32 pad3;
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u16 bytes;
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u8 rburst;
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u8 wburst;
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u16 bytes_xferred; /* 16 bits, bytes xferred */
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/* bit 0: error
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* bit 1: length error
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* bit 2: crc error
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* bit 3: truncated error
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* bit 4: phy error
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* bit 5: collision error
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* bit 6: reserved
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* bit 7: status eop for recv case
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*/
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u8 status;
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/* bit 0: eop
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* bit 1: read_fixed
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* bit 2: write fixed
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* bits 3,4,5,6: Channel (always 0)
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* bit 7: hardware owned
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*/
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u8 control;
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} __packed;
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#define SGDMA_DESC_LEN sizeof(struct sgdma_descrip)
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#define SGDMA_STATUS_ERR BIT(0)
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#define SGDMA_STATUS_LENGTH_ERR BIT(1)
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#define SGDMA_STATUS_CRC_ERR BIT(2)
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#define SGDMA_STATUS_TRUNC_ERR BIT(3)
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#define SGDMA_STATUS_PHY_ERR BIT(4)
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#define SGDMA_STATUS_COLL_ERR BIT(5)
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#define SGDMA_STATUS_EOP BIT(7)
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#define SGDMA_CONTROL_EOP BIT(0)
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#define SGDMA_CONTROL_RD_FIXED BIT(1)
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#define SGDMA_CONTROL_WR_FIXED BIT(2)
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/* Channel is always 0, so just zero initialize it */
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#define SGDMA_CONTROL_HW_OWNED BIT(7)
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/* SGDMA register space */
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struct sgdma_csr {
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/* bit 0: error
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* bit 1: eop
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* bit 2: descriptor completed
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* bit 3: chain completed
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* bit 4: busy
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* remainder reserved
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*/
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u32 status;
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u32 pad1[3];
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/* bit 0: interrupt on error
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* bit 1: interrupt on eop
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* bit 2: interrupt after every descriptor
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* bit 3: interrupt after last descrip in a chain
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* bit 4: global interrupt enable
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* bit 5: starts descriptor processing
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* bit 6: stop core on dma error
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* bit 7: interrupt on max descriptors
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* bits 8-15: max descriptors to generate interrupt
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* bit 16: Software reset
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* bit 17: clears owned by hardware if 0, does not clear otherwise
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* bit 18: enables descriptor polling mode
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* bit 19-26: clocks before polling again
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* bit 27-30: reserved
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* bit 31: clear interrupt
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*/
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u32 control;
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u32 pad2[3];
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u32 next_descrip;
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u32 pad3[3];
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};
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#define sgdma_csroffs(a) (offsetof(struct sgdma_csr, a))
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#define sgdma_descroffs(a) (offsetof(struct sgdma_descrip, a))
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#define SGDMA_STSREG_ERR BIT(0) /* Error */
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#define SGDMA_STSREG_EOP BIT(1) /* EOP */
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#define SGDMA_STSREG_DESCRIP BIT(2) /* Descriptor completed */
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#define SGDMA_STSREG_CHAIN BIT(3) /* Chain completed */
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#define SGDMA_STSREG_BUSY BIT(4) /* Controller busy */
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#define SGDMA_CTRLREG_IOE BIT(0) /* Interrupt on error */
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#define SGDMA_CTRLREG_IOEOP BIT(1) /* Interrupt on EOP */
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#define SGDMA_CTRLREG_IDESCRIP BIT(2) /* Interrupt after every descriptor */
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#define SGDMA_CTRLREG_ILASTD BIT(3) /* Interrupt after last descriptor */
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#define SGDMA_CTRLREG_INTEN BIT(4) /* Global Interrupt enable */
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#define SGDMA_CTRLREG_START BIT(5) /* starts descriptor processing */
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#define SGDMA_CTRLREG_STOPERR BIT(6) /* stop on dma error */
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#define SGDMA_CTRLREG_INTMAX BIT(7) /* Interrupt on max descriptors */
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#define SGDMA_CTRLREG_RESET BIT(16)/* Software reset */
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#define SGDMA_CTRLREG_COBHW BIT(17)/* Clears owned by hardware */
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#define SGDMA_CTRLREG_POLL BIT(18)/* enables descriptor polling mode */
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#define SGDMA_CTRLREG_CLRINT BIT(31)/* Clears interrupt */
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#endif /* __ALTERA_SGDMAHW_H__ */
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