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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses the full gnu general public license is included in this distribution in the file called copying extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 9 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154042.045106120@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
269 lines
9.5 KiB
C
269 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2003 - 2009 NetXen, Inc.
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* Copyright (C) 2009 - QLogic Corporation.
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* All rights reserved.
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*/
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#ifndef __NETXEN_NIC_HW_H_
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#define __NETXEN_NIC_HW_H_
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/* Hardware memory size of 128 meg */
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#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
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struct netxen_adapter;
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#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20)
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void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
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/* Nibble or Byte mode for phy interface (GbE mode only) */
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#define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1)
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/*
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* NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
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*
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* Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
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* Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
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* Bit 2 : enable_rx => 1:enable frame recv, 0:disable
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* Bit 3 : rx_synced => R/O: recv enable synched to recv stream
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* Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
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* Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
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* Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
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* Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
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* Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
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* Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
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* Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
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* Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
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*/
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#define netxen_gb_tx_flowctl(config_word) \
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((config_word) |= 1 << 4)
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#define netxen_gb_rx_flowctl(config_word) \
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((config_word) |= 1 << 5)
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#define netxen_gb_tx_reset_pb(config_word) \
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((config_word) |= 1 << 16)
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#define netxen_gb_rx_reset_pb(config_word) \
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((config_word) |= 1 << 17)
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#define netxen_gb_tx_reset_mac(config_word) \
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((config_word) |= 1 << 18)
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#define netxen_gb_rx_reset_mac(config_word) \
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((config_word) |= 1 << 19)
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#define netxen_gb_unset_tx_flowctl(config_word) \
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((config_word) &= ~(1 << 4))
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#define netxen_gb_unset_rx_flowctl(config_word) \
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((config_word) &= ~(1 << 5))
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#define netxen_gb_get_tx_synced(config_word) \
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_netxen_crb_get_bit((config_word), 1)
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#define netxen_gb_get_rx_synced(config_word) \
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_netxen_crb_get_bit((config_word), 3)
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#define netxen_gb_get_tx_flowctl(config_word) \
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_netxen_crb_get_bit((config_word), 4)
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#define netxen_gb_get_rx_flowctl(config_word) \
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_netxen_crb_get_bit((config_word), 5)
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#define netxen_gb_get_soft_reset(config_word) \
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_netxen_crb_get_bit((config_word), 31)
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#define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
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#define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \
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((config_word) |= ((val) & 0x07))
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#define netxen_gb_mii_mgmt_reset(config_word) \
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((config_word) |= 1 << 31)
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#define netxen_gb_mii_mgmt_unset(config_word) \
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((config_word) &= ~(1 << 31))
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/*
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* NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
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* Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
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* Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
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*/
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#define netxen_gb_mii_mgmt_set_read_cycle(config_word) \
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((config_word) |= 1 << 0)
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#define netxen_gb_mii_mgmt_reg_addr(config_word, val) \
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((config_word) |= ((val) & 0x1F))
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#define netxen_gb_mii_mgmt_phy_addr(config_word, val) \
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((config_word) |= (((val) & 0x1F) << 8))
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/*
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* NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
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* Read-only register.
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* Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
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* Bit 1 : scanning => 1:scan operation in progress, 0:idle
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* Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
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*/
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#define netxen_get_gb_mii_mgmt_busy(config_word) \
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_netxen_crb_get_bit(config_word, 0)
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#define netxen_get_gb_mii_mgmt_scanning(config_word) \
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_netxen_crb_get_bit(config_word, 1)
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#define netxen_get_gb_mii_mgmt_notvalid(config_word) \
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_netxen_crb_get_bit(config_word, 2)
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/*
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* NIU XG Pause Ctl Register
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*
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* Bit 0 : xg0_mask => 1:disable tx pause frames
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* Bit 1 : xg0_request => 1:request single pause frame
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* Bit 2 : xg0_on_off => 1:request is pause on, 0:off
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* Bit 3 : xg1_mask => 1:disable tx pause frames
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* Bit 4 : xg1_request => 1:request single pause frame
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* Bit 5 : xg1_on_off => 1:request is pause on, 0:off
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*/
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#define netxen_xg_set_xg0_mask(config_word) \
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((config_word) |= 1 << 0)
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#define netxen_xg_set_xg1_mask(config_word) \
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((config_word) |= 1 << 3)
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#define netxen_xg_get_xg0_mask(config_word) \
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_netxen_crb_get_bit((config_word), 0)
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#define netxen_xg_get_xg1_mask(config_word) \
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_netxen_crb_get_bit((config_word), 3)
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#define netxen_xg_unset_xg0_mask(config_word) \
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((config_word) &= ~(1 << 0))
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#define netxen_xg_unset_xg1_mask(config_word) \
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((config_word) &= ~(1 << 3))
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/*
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* NIU XG Pause Ctl Register
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*
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* Bit 0 : xg0_mask => 1:disable tx pause frames
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* Bit 1 : xg0_request => 1:request single pause frame
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* Bit 2 : xg0_on_off => 1:request is pause on, 0:off
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* Bit 3 : xg1_mask => 1:disable tx pause frames
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* Bit 4 : xg1_request => 1:request single pause frame
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* Bit 5 : xg1_on_off => 1:request is pause on, 0:off
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*/
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#define netxen_gb_set_gb0_mask(config_word) \
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((config_word) |= 1 << 0)
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#define netxen_gb_set_gb1_mask(config_word) \
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((config_word) |= 1 << 2)
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#define netxen_gb_set_gb2_mask(config_word) \
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((config_word) |= 1 << 4)
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#define netxen_gb_set_gb3_mask(config_word) \
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((config_word) |= 1 << 6)
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#define netxen_gb_get_gb0_mask(config_word) \
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_netxen_crb_get_bit((config_word), 0)
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#define netxen_gb_get_gb1_mask(config_word) \
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_netxen_crb_get_bit((config_word), 2)
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#define netxen_gb_get_gb2_mask(config_word) \
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_netxen_crb_get_bit((config_word), 4)
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#define netxen_gb_get_gb3_mask(config_word) \
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_netxen_crb_get_bit((config_word), 6)
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#define netxen_gb_unset_gb0_mask(config_word) \
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((config_word) &= ~(1 << 0))
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#define netxen_gb_unset_gb1_mask(config_word) \
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((config_word) &= ~(1 << 2))
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#define netxen_gb_unset_gb2_mask(config_word) \
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((config_word) &= ~(1 << 4))
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#define netxen_gb_unset_gb3_mask(config_word) \
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((config_word) &= ~(1 << 6))
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/*
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* PHY-Specific MII control/status registers.
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*/
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL 0
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS 1
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 2
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 3
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG 4
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART 5
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE 6
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT 7
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE 8
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL 9
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS 10
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS 15
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL 16
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE 18
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS 19
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE 20
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT 21
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL 24
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE 25
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET 26
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#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE 27
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/*
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* PHY-Specific Status Register (reg 17).
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*
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* Bit 0 : jabber => 1:jabber detected, 0:not
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* Bit 1 : polarity => 1:polarity reversed, 0:normal
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* Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
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* Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
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* Bit 4 : energydetect => 1:sleep, 0:active
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* Bit 5 : downshift => 1:downshift, 0:no downshift
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* Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
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* Bits 7-9 : cablelen => not valid in 10Mb/s mode
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* 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
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* Bit 10 : link => 1:link up, 0:link down
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* Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
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* Bit 12 : pagercvd => 1:page received, 0:page not received
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* Bit 13 : duplex => 1:full duplex, 0:half duplex
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* Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
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*/
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#define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
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#define netxen_set_phy_speed(config_word, val) \
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((config_word) |= ((val & 0x03) << 14))
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#define netxen_set_phy_duplex(config_word) \
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((config_word) |= 1 << 13)
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#define netxen_clear_phy_duplex(config_word) \
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((config_word) &= ~(1 << 13))
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#define netxen_get_phy_link(config_word) \
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_netxen_crb_get_bit(config_word, 10)
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#define netxen_get_phy_duplex(config_word) \
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_netxen_crb_get_bit(config_word, 13)
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/*
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* NIU Mode Register.
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* Bit 0 : enable FibreChannel
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* Bit 1 : enable 10/100/1000 Ethernet
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* Bit 2 : enable 10Gb Ethernet
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*/
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#define netxen_get_niu_enable_ge(config_word) \
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_netxen_crb_get_bit(config_word, 1)
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#define NETXEN_NIU_NON_PROMISC_MODE 0
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#define NETXEN_NIU_PROMISC_MODE 1
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#define NETXEN_NIU_ALLMULTI_MODE 2
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/*
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* NIU XG MAC Config Register
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*
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* Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
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* Bit 2 : rx_enable => 1:enable frame recv, 0:disable
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* Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
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* Bit 27: xaui_framer_reset
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* Bit 28: xaui_rx_reset
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* Bit 29: xaui_tx_reset
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* Bit 30: xg_ingress_afifo_reset
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* Bit 31: xg_egress_afifo_reset
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*/
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#define netxen_xg_soft_reset(config_word) \
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((config_word) |= 1 << 4)
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typedef struct {
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unsigned valid;
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unsigned start_128M;
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unsigned end_128M;
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unsigned start_2M;
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} crb_128M_2M_sub_block_map_t;
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typedef struct {
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crb_128M_2M_sub_block_map_t sub_block[16];
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} crb_128M_2M_block_map_t;
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#endif /* __NETXEN_NIC_HW_H_ */
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