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![Toke Høiland-Jørgensen](/assets/img/avatar_default.png)
The cpsw driver has rcu_read_lock()/rcu_read_unlock() pairs around XDP program invocations. However, the actual lifetime of the objects referred by the XDP program invocation is longer, all the way through to the call to xdp_do_flush(), making the scope of the rcu_read_lock() too small. This turns out to be harmless because it all happens in a single NAPI poll cycle (and thus under local_bh_disable()), but it makes the rcu_read_lock() misleading. Rather than extend the scope of the rcu_read_lock(), just get rid of it entirely. With the addition of RCU annotations to the XDP_REDIRECT map types that take bh execution into account, lockdep even understands this to be safe, so there's really no reason to keep it around. Signed-off-by: Toke Høiland-Jørgensen <toke@redhat.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Cc: linux-omap@vger.kernel.org Link: https://lore.kernel.org/bpf/20210624160609.292325-20-toke@redhat.com
1381 lines
32 KiB
C
1381 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Texas Instruments Ethernet Switch Driver
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*
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* Copyright (C) 2019 Texas Instruments
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*/
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#include <linux/bpf.h>
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#include <linux/bpf_trace.h>
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#include <linux/if_ether.h>
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#include <linux/if_vlan.h>
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#include <linux/kmemleak.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/net_tstamp.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/skbuff.h>
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#include <net/page_pool.h>
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#include <net/pkt_cls.h>
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#include "cpsw.h"
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#include "cpts.h"
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#include "cpsw_ale.h"
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#include "cpsw_priv.h"
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#include "cpsw_sl.h"
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#include "davinci_cpdma.h"
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#define CPTS_N_ETX_TS 4
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int (*cpsw_slave_index)(struct cpsw_common *cpsw, struct cpsw_priv *priv);
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void cpsw_intr_enable(struct cpsw_common *cpsw)
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{
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writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
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writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
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cpdma_ctlr_int_ctrl(cpsw->dma, true);
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}
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void cpsw_intr_disable(struct cpsw_common *cpsw)
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{
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writel_relaxed(0, &cpsw->wr_regs->tx_en);
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writel_relaxed(0, &cpsw->wr_regs->rx_en);
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cpdma_ctlr_int_ctrl(cpsw->dma, false);
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}
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void cpsw_tx_handler(void *token, int len, int status)
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{
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struct cpsw_meta_xdp *xmeta;
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struct xdp_frame *xdpf;
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struct net_device *ndev;
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struct netdev_queue *txq;
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struct sk_buff *skb;
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int ch;
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if (cpsw_is_xdpf_handle(token)) {
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xdpf = cpsw_handle_to_xdpf(token);
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xmeta = (void *)xdpf + CPSW_XMETA_OFFSET;
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ndev = xmeta->ndev;
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ch = xmeta->ch;
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xdp_return_frame(xdpf);
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} else {
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skb = token;
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ndev = skb->dev;
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ch = skb_get_queue_mapping(skb);
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cpts_tx_timestamp(ndev_to_cpsw(ndev)->cpts, skb);
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dev_kfree_skb_any(skb);
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}
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/* Check whether the queue is stopped due to stalled tx dma, if the
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* queue is stopped then start the queue as we have free desc for tx
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*/
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txq = netdev_get_tx_queue(ndev, ch);
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if (unlikely(netif_tx_queue_stopped(txq)))
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netif_tx_wake_queue(txq);
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ndev->stats.tx_packets++;
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ndev->stats.tx_bytes += len;
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}
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irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
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{
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struct cpsw_common *cpsw = dev_id;
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writel(0, &cpsw->wr_regs->tx_en);
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cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
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if (cpsw->quirk_irq) {
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disable_irq_nosync(cpsw->irqs_table[1]);
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cpsw->tx_irq_disabled = true;
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}
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napi_schedule(&cpsw->napi_tx);
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return IRQ_HANDLED;
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}
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irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
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{
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struct cpsw_common *cpsw = dev_id;
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writel(0, &cpsw->wr_regs->rx_en);
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cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
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if (cpsw->quirk_irq) {
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disable_irq_nosync(cpsw->irqs_table[0]);
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cpsw->rx_irq_disabled = true;
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}
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napi_schedule(&cpsw->napi_rx);
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return IRQ_HANDLED;
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}
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irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id)
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{
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struct cpsw_common *cpsw = dev_id;
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writel(0, &cpsw->wr_regs->misc_en);
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cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_MISC);
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cpts_misc_interrupt(cpsw->cpts);
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writel(0x10, &cpsw->wr_regs->misc_en);
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return IRQ_HANDLED;
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}
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int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
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{
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struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
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int num_tx, cur_budget, ch;
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u32 ch_map;
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struct cpsw_vector *txv;
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/* process every unprocessed channel */
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ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
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for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) {
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if (!(ch_map & 0x80))
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continue;
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txv = &cpsw->txv[ch];
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if (unlikely(txv->budget > budget - num_tx))
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cur_budget = budget - num_tx;
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else
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cur_budget = txv->budget;
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num_tx += cpdma_chan_process(txv->ch, cur_budget);
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if (num_tx >= budget)
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break;
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}
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if (num_tx < budget) {
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napi_complete(napi_tx);
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writel(0xff, &cpsw->wr_regs->tx_en);
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}
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return num_tx;
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}
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int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
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{
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struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
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int num_tx;
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num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
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if (num_tx < budget) {
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napi_complete(napi_tx);
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writel(0xff, &cpsw->wr_regs->tx_en);
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if (cpsw->tx_irq_disabled) {
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cpsw->tx_irq_disabled = false;
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enable_irq(cpsw->irqs_table[1]);
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}
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}
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return num_tx;
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}
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int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget)
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{
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struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
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int num_rx, cur_budget, ch;
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u32 ch_map;
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struct cpsw_vector *rxv;
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/* process every unprocessed channel */
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ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
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for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
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if (!(ch_map & 0x01))
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continue;
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rxv = &cpsw->rxv[ch];
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if (unlikely(rxv->budget > budget - num_rx))
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cur_budget = budget - num_rx;
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else
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cur_budget = rxv->budget;
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num_rx += cpdma_chan_process(rxv->ch, cur_budget);
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if (num_rx >= budget)
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break;
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}
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if (num_rx < budget) {
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napi_complete_done(napi_rx, num_rx);
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writel(0xff, &cpsw->wr_regs->rx_en);
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}
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return num_rx;
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}
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int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
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{
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struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
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int num_rx;
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num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
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if (num_rx < budget) {
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napi_complete_done(napi_rx, num_rx);
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writel(0xff, &cpsw->wr_regs->rx_en);
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if (cpsw->rx_irq_disabled) {
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cpsw->rx_irq_disabled = false;
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enable_irq(cpsw->irqs_table[0]);
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}
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}
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return num_rx;
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}
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void cpsw_rx_vlan_encap(struct sk_buff *skb)
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{
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struct cpsw_priv *priv = netdev_priv(skb->dev);
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u32 rx_vlan_encap_hdr = *((u32 *)skb->data);
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struct cpsw_common *cpsw = priv->cpsw;
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u16 vtag, vid, prio, pkt_type;
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/* Remove VLAN header encapsulation word */
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skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE);
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pkt_type = (rx_vlan_encap_hdr >>
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CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) &
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CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK;
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/* Ignore unknown & Priority-tagged packets*/
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if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV ||
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pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG)
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return;
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vid = (rx_vlan_encap_hdr >>
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CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) &
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VLAN_VID_MASK;
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/* Ignore vid 0 and pass packet as is */
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if (!vid)
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return;
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/* Untag P0 packets if set for vlan */
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if (!cpsw_ale_get_vlan_p0_untag(cpsw->ale, vid)) {
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prio = (rx_vlan_encap_hdr >>
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CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) &
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CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK;
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vtag = (prio << VLAN_PRIO_SHIFT) | vid;
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__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
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}
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/* strip vlan tag for VLAN-tagged packet */
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if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) {
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memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN);
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skb_pull(skb, VLAN_HLEN);
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}
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}
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void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv)
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{
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slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
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slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
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}
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void soft_reset(const char *module, void __iomem *reg)
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{
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unsigned long timeout = jiffies + HZ;
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writel_relaxed(1, reg);
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do {
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cpu_relax();
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} while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
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WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
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}
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void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue)
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{
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struct cpsw_priv *priv = netdev_priv(ndev);
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struct cpsw_common *cpsw = priv->cpsw;
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int ch;
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cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
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ndev->stats.tx_errors++;
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cpsw_intr_disable(cpsw);
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for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
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cpdma_chan_stop(cpsw->txv[ch].ch);
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cpdma_chan_start(cpsw->txv[ch].ch);
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}
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cpsw_intr_enable(cpsw);
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netif_trans_update(ndev);
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netif_tx_wake_all_queues(ndev);
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}
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static int cpsw_get_common_speed(struct cpsw_common *cpsw)
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{
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int i, speed;
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for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
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if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
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speed += cpsw->slaves[i].phy->speed;
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return speed;
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}
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int cpsw_need_resplit(struct cpsw_common *cpsw)
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{
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int i, rlim_ch_num;
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int speed, ch_rate;
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/* re-split resources only in case speed was changed */
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speed = cpsw_get_common_speed(cpsw);
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if (speed == cpsw->speed || !speed)
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return 0;
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cpsw->speed = speed;
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for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
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ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
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if (!ch_rate)
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break;
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rlim_ch_num++;
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}
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/* cases not dependent on speed */
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if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
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return 0;
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return 1;
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}
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void cpsw_split_res(struct cpsw_common *cpsw)
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{
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u32 consumed_rate = 0, bigest_rate = 0;
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struct cpsw_vector *txv = cpsw->txv;
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int i, ch_weight, rlim_ch_num = 0;
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int budget, bigest_rate_ch = 0;
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u32 ch_rate, max_rate;
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int ch_budget = 0;
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for (i = 0; i < cpsw->tx_ch_num; i++) {
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ch_rate = cpdma_chan_get_rate(txv[i].ch);
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if (!ch_rate)
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continue;
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rlim_ch_num++;
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consumed_rate += ch_rate;
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}
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if (cpsw->tx_ch_num == rlim_ch_num) {
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max_rate = consumed_rate;
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} else if (!rlim_ch_num) {
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ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
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bigest_rate = 0;
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max_rate = consumed_rate;
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} else {
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max_rate = cpsw->speed * 1000;
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/* if max_rate is less then expected due to reduced link speed,
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* split proportionally according next potential max speed
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*/
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if (max_rate < consumed_rate)
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max_rate *= 10;
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if (max_rate < consumed_rate)
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max_rate *= 10;
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ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
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ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
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(cpsw->tx_ch_num - rlim_ch_num);
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bigest_rate = (max_rate - consumed_rate) /
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(cpsw->tx_ch_num - rlim_ch_num);
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}
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/* split tx weight/budget */
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budget = CPSW_POLL_WEIGHT;
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for (i = 0; i < cpsw->tx_ch_num; i++) {
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ch_rate = cpdma_chan_get_rate(txv[i].ch);
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if (ch_rate) {
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txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
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if (!txv[i].budget)
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txv[i].budget++;
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if (ch_rate > bigest_rate) {
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bigest_rate_ch = i;
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bigest_rate = ch_rate;
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}
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ch_weight = (ch_rate * 100) / max_rate;
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if (!ch_weight)
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ch_weight++;
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cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
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} else {
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txv[i].budget = ch_budget;
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if (!bigest_rate_ch)
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bigest_rate_ch = i;
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cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
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}
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budget -= txv[i].budget;
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}
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if (budget)
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txv[bigest_rate_ch].budget += budget;
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/* split rx budget */
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budget = CPSW_POLL_WEIGHT;
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ch_budget = budget / cpsw->rx_ch_num;
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for (i = 0; i < cpsw->rx_ch_num; i++) {
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cpsw->rxv[i].budget = ch_budget;
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budget -= ch_budget;
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}
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if (budget)
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cpsw->rxv[0].budget += budget;
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}
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int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
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int ale_ageout, phys_addr_t desc_mem_phys,
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int descs_pool_size)
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{
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u32 slave_offset, sliver_offset, slave_size;
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struct cpsw_ale_params ale_params;
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struct cpsw_platform_data *data;
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struct cpdma_params dma_params;
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struct device *dev = cpsw->dev;
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struct device_node *cpts_node;
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void __iomem *cpts_regs;
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int ret = 0, i;
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data = &cpsw->data;
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cpsw->rx_ch_num = 1;
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cpsw->tx_ch_num = 1;
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cpsw->version = readl(&cpsw->regs->id_ver);
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memset(&dma_params, 0, sizeof(dma_params));
|
|
memset(&ale_params, 0, sizeof(ale_params));
|
|
|
|
switch (cpsw->version) {
|
|
case CPSW_VERSION_1:
|
|
cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
|
|
cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
|
|
cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
|
|
dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
|
|
dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
|
|
ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
|
|
slave_offset = CPSW1_SLAVE_OFFSET;
|
|
slave_size = CPSW1_SLAVE_SIZE;
|
|
sliver_offset = CPSW1_SLIVER_OFFSET;
|
|
dma_params.desc_mem_phys = 0;
|
|
break;
|
|
case CPSW_VERSION_2:
|
|
case CPSW_VERSION_3:
|
|
case CPSW_VERSION_4:
|
|
cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
|
|
cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
|
|
cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
|
|
dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
|
|
dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
|
|
ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
|
|
slave_offset = CPSW2_SLAVE_OFFSET;
|
|
slave_size = CPSW2_SLAVE_SIZE;
|
|
sliver_offset = CPSW2_SLIVER_OFFSET;
|
|
dma_params.desc_mem_phys = desc_mem_phys;
|
|
break;
|
|
default:
|
|
dev_err(dev, "unknown version 0x%08x\n", cpsw->version);
|
|
return -ENODEV;
|
|
}
|
|
|
|
for (i = 0; i < cpsw->data.slaves; i++) {
|
|
struct cpsw_slave *slave = &cpsw->slaves[i];
|
|
void __iomem *regs = cpsw->regs;
|
|
|
|
slave->slave_num = i;
|
|
slave->data = &cpsw->data.slave_data[i];
|
|
slave->regs = regs + slave_offset;
|
|
slave->port_vlan = slave->data->dual_emac_res_vlan;
|
|
slave->mac_sl = cpsw_sl_get("cpsw", dev, regs + sliver_offset);
|
|
if (IS_ERR(slave->mac_sl))
|
|
return PTR_ERR(slave->mac_sl);
|
|
|
|
slave_offset += slave_size;
|
|
sliver_offset += SLIVER_SIZE;
|
|
}
|
|
|
|
ale_params.dev = dev;
|
|
ale_params.ale_ageout = ale_ageout;
|
|
ale_params.ale_ports = CPSW_ALE_PORTS_NUM;
|
|
ale_params.dev_id = "cpsw";
|
|
|
|
cpsw->ale = cpsw_ale_create(&ale_params);
|
|
if (IS_ERR(cpsw->ale)) {
|
|
dev_err(dev, "error initializing ale engine\n");
|
|
return PTR_ERR(cpsw->ale);
|
|
}
|
|
|
|
dma_params.dev = dev;
|
|
dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
|
|
dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
|
|
dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
|
|
dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
|
|
dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
|
|
|
|
dma_params.num_chan = data->channels;
|
|
dma_params.has_soft_reset = true;
|
|
dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
|
|
dma_params.desc_mem_size = data->bd_ram_size;
|
|
dma_params.desc_align = 16;
|
|
dma_params.has_ext_regs = true;
|
|
dma_params.desc_hw_addr = dma_params.desc_mem_phys;
|
|
dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
|
|
dma_params.descs_pool_size = descs_pool_size;
|
|
|
|
cpsw->dma = cpdma_ctlr_create(&dma_params);
|
|
if (!cpsw->dma) {
|
|
dev_err(dev, "error initializing dma\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
cpts_node = of_get_child_by_name(cpsw->dev->of_node, "cpts");
|
|
if (!cpts_node)
|
|
cpts_node = cpsw->dev->of_node;
|
|
|
|
cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpts_node,
|
|
CPTS_N_ETX_TS);
|
|
if (IS_ERR(cpsw->cpts)) {
|
|
ret = PTR_ERR(cpsw->cpts);
|
|
cpdma_ctlr_destroy(cpsw->dma);
|
|
}
|
|
of_node_put(cpts_node);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_TI_CPTS)
|
|
|
|
static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct cpsw_slave *slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
|
|
u32 ts_en, seq_id;
|
|
|
|
if (!priv->tx_ts_enabled && !priv->rx_ts_enabled) {
|
|
slave_write(slave, 0, CPSW1_TS_CTL);
|
|
return;
|
|
}
|
|
|
|
seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
|
|
ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
|
|
|
|
if (priv->tx_ts_enabled)
|
|
ts_en |= CPSW_V1_TS_TX_EN;
|
|
|
|
if (priv->rx_ts_enabled)
|
|
ts_en |= CPSW_V1_TS_RX_EN;
|
|
|
|
slave_write(slave, ts_en, CPSW1_TS_CTL);
|
|
slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
|
|
}
|
|
|
|
static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct cpsw_slave *slave;
|
|
u32 ctrl, mtype;
|
|
|
|
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
|
|
|
|
ctrl = slave_read(slave, CPSW2_CONTROL);
|
|
switch (cpsw->version) {
|
|
case CPSW_VERSION_2:
|
|
ctrl &= ~CTRL_V2_ALL_TS_MASK;
|
|
|
|
if (priv->tx_ts_enabled)
|
|
ctrl |= CTRL_V2_TX_TS_BITS;
|
|
|
|
if (priv->rx_ts_enabled)
|
|
ctrl |= CTRL_V2_RX_TS_BITS;
|
|
break;
|
|
case CPSW_VERSION_3:
|
|
default:
|
|
ctrl &= ~CTRL_V3_ALL_TS_MASK;
|
|
|
|
if (priv->tx_ts_enabled)
|
|
ctrl |= CTRL_V3_TX_TS_BITS;
|
|
|
|
if (priv->rx_ts_enabled)
|
|
ctrl |= CTRL_V3_RX_TS_BITS;
|
|
break;
|
|
}
|
|
|
|
mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
|
|
|
|
slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
|
|
slave_write(slave, ctrl, CPSW2_CONTROL);
|
|
writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
|
|
writel_relaxed(ETH_P_8021Q, &cpsw->regs->vlan_ltype);
|
|
}
|
|
|
|
static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
|
|
{
|
|
struct cpsw_priv *priv = netdev_priv(dev);
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct hwtstamp_config cfg;
|
|
|
|
if (cpsw->version != CPSW_VERSION_1 &&
|
|
cpsw->version != CPSW_VERSION_2 &&
|
|
cpsw->version != CPSW_VERSION_3)
|
|
return -EOPNOTSUPP;
|
|
|
|
if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
|
|
return -EFAULT;
|
|
|
|
/* reserved for future extensions */
|
|
if (cfg.flags)
|
|
return -EINVAL;
|
|
|
|
if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
|
|
return -ERANGE;
|
|
|
|
switch (cfg.rx_filter) {
|
|
case HWTSTAMP_FILTER_NONE:
|
|
priv->rx_ts_enabled = 0;
|
|
break;
|
|
case HWTSTAMP_FILTER_ALL:
|
|
case HWTSTAMP_FILTER_NTP_ALL:
|
|
case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
|
|
case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
|
|
case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
|
|
return -ERANGE;
|
|
case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
|
|
case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
|
|
case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
|
|
case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
|
|
case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
|
|
case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
|
|
case HWTSTAMP_FILTER_PTP_V2_EVENT:
|
|
case HWTSTAMP_FILTER_PTP_V2_SYNC:
|
|
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
|
|
priv->rx_ts_enabled = HWTSTAMP_FILTER_PTP_V2_EVENT;
|
|
cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
|
|
break;
|
|
default:
|
|
return -ERANGE;
|
|
}
|
|
|
|
priv->tx_ts_enabled = cfg.tx_type == HWTSTAMP_TX_ON;
|
|
|
|
switch (cpsw->version) {
|
|
case CPSW_VERSION_1:
|
|
cpsw_hwtstamp_v1(priv);
|
|
break;
|
|
case CPSW_VERSION_2:
|
|
case CPSW_VERSION_3:
|
|
cpsw_hwtstamp_v2(priv);
|
|
break;
|
|
default:
|
|
WARN_ON(1);
|
|
}
|
|
|
|
return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
|
|
}
|
|
|
|
static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
|
|
{
|
|
struct cpsw_common *cpsw = ndev_to_cpsw(dev);
|
|
struct cpsw_priv *priv = netdev_priv(dev);
|
|
struct hwtstamp_config cfg;
|
|
|
|
if (cpsw->version != CPSW_VERSION_1 &&
|
|
cpsw->version != CPSW_VERSION_2 &&
|
|
cpsw->version != CPSW_VERSION_3)
|
|
return -EOPNOTSUPP;
|
|
|
|
cfg.flags = 0;
|
|
cfg.tx_type = priv->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
|
|
cfg.rx_filter = priv->rx_ts_enabled;
|
|
|
|
return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
|
|
}
|
|
#else
|
|
static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
|
|
{
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
|
|
{
|
|
return -EOPNOTSUPP;
|
|
}
|
|
#endif /*CONFIG_TI_CPTS*/
|
|
|
|
int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
|
|
{
|
|
struct cpsw_priv *priv = netdev_priv(dev);
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
int slave_no = cpsw_slave_index(cpsw, priv);
|
|
|
|
if (!netif_running(dev))
|
|
return -EINVAL;
|
|
|
|
switch (cmd) {
|
|
case SIOCSHWTSTAMP:
|
|
return cpsw_hwtstamp_set(dev, req);
|
|
case SIOCGHWTSTAMP:
|
|
return cpsw_hwtstamp_get(dev, req);
|
|
}
|
|
|
|
if (!cpsw->slaves[slave_no].phy)
|
|
return -EOPNOTSUPP;
|
|
return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
|
|
}
|
|
|
|
int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
|
|
{
|
|
struct cpsw_priv *priv = netdev_priv(ndev);
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct cpsw_slave *slave;
|
|
u32 min_rate;
|
|
u32 ch_rate;
|
|
int i, ret;
|
|
|
|
ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
|
|
if (ch_rate == rate)
|
|
return 0;
|
|
|
|
ch_rate = rate * 1000;
|
|
min_rate = cpdma_chan_get_min_rate(cpsw->dma);
|
|
if ((ch_rate < min_rate && ch_rate)) {
|
|
dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
|
|
min_rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (rate > cpsw->speed) {
|
|
dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = pm_runtime_get_sync(cpsw->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(cpsw->dev);
|
|
return ret;
|
|
}
|
|
|
|
ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
|
|
pm_runtime_put(cpsw->dev);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* update rates for slaves tx queues */
|
|
for (i = 0; i < cpsw->data.slaves; i++) {
|
|
slave = &cpsw->slaves[i];
|
|
if (!slave->ndev)
|
|
continue;
|
|
|
|
netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
|
|
}
|
|
|
|
cpsw_split_res(cpsw);
|
|
return ret;
|
|
}
|
|
|
|
static int cpsw_tc_to_fifo(int tc, int num_tc)
|
|
{
|
|
if (tc == num_tc - 1)
|
|
return 0;
|
|
|
|
return CPSW_FIFO_SHAPERS_NUM - tc;
|
|
}
|
|
|
|
bool cpsw_shp_is_off(struct cpsw_priv *priv)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct cpsw_slave *slave;
|
|
u32 shift, mask, val;
|
|
|
|
val = readl_relaxed(&cpsw->regs->ptype);
|
|
|
|
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
|
|
shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
|
|
mask = 7 << shift;
|
|
val = val & mask;
|
|
|
|
return !val;
|
|
}
|
|
|
|
static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct cpsw_slave *slave;
|
|
u32 shift, mask, val;
|
|
|
|
val = readl_relaxed(&cpsw->regs->ptype);
|
|
|
|
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
|
|
shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
|
|
mask = (1 << --fifo) << shift;
|
|
val = on ? val | mask : val & ~mask;
|
|
|
|
writel_relaxed(val, &cpsw->regs->ptype);
|
|
}
|
|
|
|
static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
u32 val = 0, send_pct, shift;
|
|
struct cpsw_slave *slave;
|
|
int pct = 0, i;
|
|
|
|
if (bw > priv->shp_cfg_speed * 1000)
|
|
goto err;
|
|
|
|
/* shaping has to stay enabled for highest fifos linearly
|
|
* and fifo bw no more then interface can allow
|
|
*/
|
|
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
|
|
send_pct = slave_read(slave, SEND_PERCENT);
|
|
for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) {
|
|
if (!bw) {
|
|
if (i >= fifo || !priv->fifo_bw[i])
|
|
continue;
|
|
|
|
dev_warn(priv->dev, "Prev FIFO%d is shaped", i);
|
|
continue;
|
|
}
|
|
|
|
if (!priv->fifo_bw[i] && i > fifo) {
|
|
dev_err(priv->dev, "Upper FIFO%d is not shaped", i);
|
|
return -EINVAL;
|
|
}
|
|
|
|
shift = (i - 1) * 8;
|
|
if (i == fifo) {
|
|
send_pct &= ~(CPSW_PCT_MASK << shift);
|
|
val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10);
|
|
if (!val)
|
|
val = 1;
|
|
|
|
send_pct |= val << shift;
|
|
pct += val;
|
|
continue;
|
|
}
|
|
|
|
if (priv->fifo_bw[i])
|
|
pct += (send_pct >> shift) & CPSW_PCT_MASK;
|
|
}
|
|
|
|
if (pct >= 100)
|
|
goto err;
|
|
|
|
slave_write(slave, send_pct, SEND_PERCENT);
|
|
priv->fifo_bw[fifo] = bw;
|
|
|
|
dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo,
|
|
DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100));
|
|
|
|
return 0;
|
|
err:
|
|
dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration");
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct cpsw_slave *slave;
|
|
u32 tx_in_ctl_rg, val;
|
|
int ret;
|
|
|
|
ret = cpsw_set_fifo_bw(priv, fifo, bw);
|
|
if (ret)
|
|
return ret;
|
|
|
|
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
|
|
tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ?
|
|
CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL;
|
|
|
|
if (!bw)
|
|
cpsw_fifo_shp_on(priv, fifo, bw);
|
|
|
|
val = slave_read(slave, tx_in_ctl_rg);
|
|
if (cpsw_shp_is_off(priv)) {
|
|
/* disable FIFOs rate limited queues */
|
|
val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT);
|
|
|
|
/* set type of FIFO queues to normal priority mode */
|
|
val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT);
|
|
|
|
/* set type of FIFO queues to be rate limited */
|
|
if (bw)
|
|
val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT;
|
|
else
|
|
priv->shp_cfg_speed = 0;
|
|
}
|
|
|
|
/* toggle a FIFO rate limited queue */
|
|
if (bw)
|
|
val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
|
|
else
|
|
val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
|
|
slave_write(slave, val, tx_in_ctl_rg);
|
|
|
|
/* FIFO transmit shape enable */
|
|
cpsw_fifo_shp_on(priv, fifo, bw);
|
|
return 0;
|
|
}
|
|
|
|
/* Defaults:
|
|
* class A - prio 3
|
|
* class B - prio 2
|
|
* shaping for class A should be set first
|
|
*/
|
|
static int cpsw_set_cbs(struct net_device *ndev,
|
|
struct tc_cbs_qopt_offload *qopt)
|
|
{
|
|
struct cpsw_priv *priv = netdev_priv(ndev);
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct cpsw_slave *slave;
|
|
int prev_speed = 0;
|
|
int tc, ret, fifo;
|
|
u32 bw = 0;
|
|
|
|
tc = netdev_txq_to_tc(priv->ndev, qopt->queue);
|
|
|
|
/* enable channels in backward order, as highest FIFOs must be rate
|
|
* limited first and for compliance with CPDMA rate limited channels
|
|
* that also used in bacward order. FIFO0 cannot be rate limited.
|
|
*/
|
|
fifo = cpsw_tc_to_fifo(tc, ndev->num_tc);
|
|
if (!fifo) {
|
|
dev_err(priv->dev, "Last tc%d can't be rate limited", tc);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* do nothing, it's disabled anyway */
|
|
if (!qopt->enable && !priv->fifo_bw[fifo])
|
|
return 0;
|
|
|
|
/* shapers can be set if link speed is known */
|
|
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
|
|
if (slave->phy && slave->phy->link) {
|
|
if (priv->shp_cfg_speed &&
|
|
priv->shp_cfg_speed != slave->phy->speed)
|
|
prev_speed = priv->shp_cfg_speed;
|
|
|
|
priv->shp_cfg_speed = slave->phy->speed;
|
|
}
|
|
|
|
if (!priv->shp_cfg_speed) {
|
|
dev_err(priv->dev, "Link speed is not known");
|
|
return -1;
|
|
}
|
|
|
|
ret = pm_runtime_get_sync(cpsw->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(cpsw->dev);
|
|
return ret;
|
|
}
|
|
|
|
bw = qopt->enable ? qopt->idleslope : 0;
|
|
ret = cpsw_set_fifo_rlimit(priv, fifo, bw);
|
|
if (ret) {
|
|
priv->shp_cfg_speed = prev_speed;
|
|
prev_speed = 0;
|
|
}
|
|
|
|
if (bw && prev_speed)
|
|
dev_warn(priv->dev,
|
|
"Speed was changed, CBS shaper speeds are changed!");
|
|
|
|
pm_runtime_put_sync(cpsw->dev);
|
|
return ret;
|
|
}
|
|
|
|
static int cpsw_set_mqprio(struct net_device *ndev, void *type_data)
|
|
{
|
|
struct tc_mqprio_qopt_offload *mqprio = type_data;
|
|
struct cpsw_priv *priv = netdev_priv(ndev);
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
int fifo, num_tc, count, offset;
|
|
struct cpsw_slave *slave;
|
|
u32 tx_prio_map = 0;
|
|
int i, tc, ret;
|
|
|
|
num_tc = mqprio->qopt.num_tc;
|
|
if (num_tc > CPSW_TC_NUM)
|
|
return -EINVAL;
|
|
|
|
if (mqprio->mode != TC_MQPRIO_MODE_DCB)
|
|
return -EINVAL;
|
|
|
|
ret = pm_runtime_get_sync(cpsw->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(cpsw->dev);
|
|
return ret;
|
|
}
|
|
|
|
if (num_tc) {
|
|
for (i = 0; i < 8; i++) {
|
|
tc = mqprio->qopt.prio_tc_map[i];
|
|
fifo = cpsw_tc_to_fifo(tc, num_tc);
|
|
tx_prio_map |= fifo << (4 * i);
|
|
}
|
|
|
|
netdev_set_num_tc(ndev, num_tc);
|
|
for (i = 0; i < num_tc; i++) {
|
|
count = mqprio->qopt.count[i];
|
|
offset = mqprio->qopt.offset[i];
|
|
netdev_set_tc_queue(ndev, i, count, offset);
|
|
}
|
|
}
|
|
|
|
if (!mqprio->qopt.hw) {
|
|
/* restore default configuration */
|
|
netdev_reset_tc(ndev);
|
|
tx_prio_map = TX_PRIORITY_MAPPING;
|
|
}
|
|
|
|
priv->mqprio_hw = mqprio->qopt.hw;
|
|
|
|
offset = cpsw->version == CPSW_VERSION_1 ?
|
|
CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
|
|
|
|
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
|
|
slave_write(slave, tx_prio_map, offset);
|
|
|
|
pm_runtime_put_sync(cpsw->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
|
|
void *type_data)
|
|
{
|
|
switch (type) {
|
|
case TC_SETUP_QDISC_CBS:
|
|
return cpsw_set_cbs(ndev, type_data);
|
|
|
|
case TC_SETUP_QDISC_MQPRIO:
|
|
return cpsw_set_mqprio(ndev, type_data);
|
|
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
|
|
{
|
|
int fifo, bw;
|
|
|
|
for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) {
|
|
bw = priv->fifo_bw[fifo];
|
|
if (!bw)
|
|
continue;
|
|
|
|
cpsw_set_fifo_rlimit(priv, fifo, bw);
|
|
}
|
|
}
|
|
|
|
void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
u32 tx_prio_map = 0;
|
|
int i, tc, fifo;
|
|
u32 tx_prio_rg;
|
|
|
|
if (!priv->mqprio_hw)
|
|
return;
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
tc = netdev_get_prio_tc_map(priv->ndev, i);
|
|
fifo = CPSW_FIFO_SHAPERS_NUM - tc;
|
|
tx_prio_map |= fifo << (4 * i);
|
|
}
|
|
|
|
tx_prio_rg = cpsw->version == CPSW_VERSION_1 ?
|
|
CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
|
|
|
|
slave_write(slave, tx_prio_map, tx_prio_rg);
|
|
}
|
|
|
|
int cpsw_fill_rx_channels(struct cpsw_priv *priv)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct cpsw_meta_xdp *xmeta;
|
|
struct page_pool *pool;
|
|
struct page *page;
|
|
int ch_buf_num;
|
|
int ch, i, ret;
|
|
dma_addr_t dma;
|
|
|
|
for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
|
|
pool = cpsw->page_pool[ch];
|
|
ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
|
|
for (i = 0; i < ch_buf_num; i++) {
|
|
page = page_pool_dev_alloc_pages(pool);
|
|
if (!page) {
|
|
cpsw_err(priv, ifup, "allocate rx page err\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
xmeta = page_address(page) + CPSW_XMETA_OFFSET;
|
|
xmeta->ndev = priv->ndev;
|
|
xmeta->ch = ch;
|
|
|
|
dma = page_pool_get_dma_addr(page) + CPSW_HEADROOM;
|
|
ret = cpdma_chan_idle_submit_mapped(cpsw->rxv[ch].ch,
|
|
page, dma,
|
|
cpsw->rx_packet_max,
|
|
0);
|
|
if (ret < 0) {
|
|
cpsw_err(priv, ifup,
|
|
"cannot submit page to channel %d rx, error %d\n",
|
|
ch, ret);
|
|
page_pool_recycle_direct(pool, page);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
|
|
ch, ch_buf_num);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct page_pool *cpsw_create_page_pool(struct cpsw_common *cpsw,
|
|
int size)
|
|
{
|
|
struct page_pool_params pp_params;
|
|
struct page_pool *pool;
|
|
|
|
pp_params.order = 0;
|
|
pp_params.flags = PP_FLAG_DMA_MAP;
|
|
pp_params.pool_size = size;
|
|
pp_params.nid = NUMA_NO_NODE;
|
|
pp_params.dma_dir = DMA_BIDIRECTIONAL;
|
|
pp_params.dev = cpsw->dev;
|
|
|
|
pool = page_pool_create(&pp_params);
|
|
if (IS_ERR(pool))
|
|
dev_err(cpsw->dev, "cannot create rx page pool\n");
|
|
|
|
return pool;
|
|
}
|
|
|
|
static int cpsw_create_rx_pool(struct cpsw_common *cpsw, int ch)
|
|
{
|
|
struct page_pool *pool;
|
|
int ret = 0, pool_size;
|
|
|
|
pool_size = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
|
|
pool = cpsw_create_page_pool(cpsw, pool_size);
|
|
if (IS_ERR(pool))
|
|
ret = PTR_ERR(pool);
|
|
else
|
|
cpsw->page_pool[ch] = pool;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int cpsw_ndev_create_xdp_rxq(struct cpsw_priv *priv, int ch)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct xdp_rxq_info *rxq;
|
|
struct page_pool *pool;
|
|
int ret;
|
|
|
|
pool = cpsw->page_pool[ch];
|
|
rxq = &priv->xdp_rxq[ch];
|
|
|
|
ret = xdp_rxq_info_reg(rxq, priv->ndev, ch, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = xdp_rxq_info_reg_mem_model(rxq, MEM_TYPE_PAGE_POOL, pool);
|
|
if (ret)
|
|
xdp_rxq_info_unreg(rxq);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void cpsw_ndev_destroy_xdp_rxq(struct cpsw_priv *priv, int ch)
|
|
{
|
|
struct xdp_rxq_info *rxq = &priv->xdp_rxq[ch];
|
|
|
|
if (!xdp_rxq_info_is_reg(rxq))
|
|
return;
|
|
|
|
xdp_rxq_info_unreg(rxq);
|
|
}
|
|
|
|
void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw)
|
|
{
|
|
struct net_device *ndev;
|
|
int i, ch;
|
|
|
|
for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
|
|
for (i = 0; i < cpsw->data.slaves; i++) {
|
|
ndev = cpsw->slaves[i].ndev;
|
|
if (!ndev)
|
|
continue;
|
|
|
|
cpsw_ndev_destroy_xdp_rxq(netdev_priv(ndev), ch);
|
|
}
|
|
|
|
page_pool_destroy(cpsw->page_pool[ch]);
|
|
cpsw->page_pool[ch] = NULL;
|
|
}
|
|
}
|
|
|
|
int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw)
|
|
{
|
|
struct net_device *ndev;
|
|
int i, ch, ret;
|
|
|
|
for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
|
|
ret = cpsw_create_rx_pool(cpsw, ch);
|
|
if (ret)
|
|
goto err_cleanup;
|
|
|
|
/* using same page pool is allowed as no running rx handlers
|
|
* simultaneously for both ndevs
|
|
*/
|
|
for (i = 0; i < cpsw->data.slaves; i++) {
|
|
ndev = cpsw->slaves[i].ndev;
|
|
if (!ndev)
|
|
continue;
|
|
|
|
ret = cpsw_ndev_create_xdp_rxq(netdev_priv(ndev), ch);
|
|
if (ret)
|
|
goto err_cleanup;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_cleanup:
|
|
cpsw_destroy_xdp_rxqs(cpsw);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int cpsw_xdp_prog_setup(struct cpsw_priv *priv, struct netdev_bpf *bpf)
|
|
{
|
|
struct bpf_prog *prog = bpf->prog;
|
|
|
|
if (!priv->xdpi.prog && !prog)
|
|
return 0;
|
|
|
|
WRITE_ONCE(priv->xdp_prog, prog);
|
|
|
|
xdp_attachment_setup(&priv->xdpi, bpf);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf)
|
|
{
|
|
struct cpsw_priv *priv = netdev_priv(ndev);
|
|
|
|
switch (bpf->command) {
|
|
case XDP_SETUP_PROG:
|
|
return cpsw_xdp_prog_setup(priv, bpf);
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf,
|
|
struct page *page, int port)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct cpsw_meta_xdp *xmeta;
|
|
struct cpdma_chan *txch;
|
|
dma_addr_t dma;
|
|
int ret;
|
|
|
|
xmeta = (void *)xdpf + CPSW_XMETA_OFFSET;
|
|
xmeta->ndev = priv->ndev;
|
|
xmeta->ch = 0;
|
|
txch = cpsw->txv[0].ch;
|
|
|
|
if (page) {
|
|
dma = page_pool_get_dma_addr(page);
|
|
dma += xdpf->headroom + sizeof(struct xdp_frame);
|
|
ret = cpdma_chan_submit_mapped(txch, cpsw_xdpf_to_handle(xdpf),
|
|
dma, xdpf->len, port);
|
|
} else {
|
|
if (sizeof(*xmeta) > xdpf->headroom)
|
|
return -EINVAL;
|
|
|
|
ret = cpdma_chan_submit(txch, cpsw_xdpf_to_handle(xdpf),
|
|
xdpf->data, xdpf->len, port);
|
|
}
|
|
|
|
if (ret)
|
|
priv->ndev->stats.tx_dropped++;
|
|
|
|
return ret;
|
|
}
|
|
|
|
int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp,
|
|
struct page *page, int port, int *len)
|
|
{
|
|
struct cpsw_common *cpsw = priv->cpsw;
|
|
struct net_device *ndev = priv->ndev;
|
|
int ret = CPSW_XDP_CONSUMED;
|
|
struct xdp_frame *xdpf;
|
|
struct bpf_prog *prog;
|
|
u32 act;
|
|
|
|
prog = READ_ONCE(priv->xdp_prog);
|
|
if (!prog)
|
|
return CPSW_XDP_PASS;
|
|
|
|
act = bpf_prog_run_xdp(prog, xdp);
|
|
/* XDP prog might have changed packet data and boundaries */
|
|
*len = xdp->data_end - xdp->data;
|
|
|
|
switch (act) {
|
|
case XDP_PASS:
|
|
ret = CPSW_XDP_PASS;
|
|
goto out;
|
|
case XDP_TX:
|
|
xdpf = xdp_convert_buff_to_frame(xdp);
|
|
if (unlikely(!xdpf))
|
|
goto drop;
|
|
|
|
if (cpsw_xdp_tx_frame(priv, xdpf, page, port))
|
|
xdp_return_frame_rx_napi(xdpf);
|
|
break;
|
|
case XDP_REDIRECT:
|
|
if (xdp_do_redirect(ndev, xdp, prog))
|
|
goto drop;
|
|
|
|
/* Have to flush here, per packet, instead of doing it in bulk
|
|
* at the end of the napi handler. The RX devices on this
|
|
* particular hardware is sharing a common queue, so the
|
|
* incoming device might change per packet.
|
|
*/
|
|
xdp_do_flush_map();
|
|
break;
|
|
default:
|
|
bpf_warn_invalid_xdp_action(act);
|
|
fallthrough;
|
|
case XDP_ABORTED:
|
|
trace_xdp_exception(ndev, prog, act);
|
|
fallthrough; /* handle aborts by dropping packet */
|
|
case XDP_DROP:
|
|
ndev->stats.rx_bytes += *len;
|
|
ndev->stats.rx_packets++;
|
|
goto drop;
|
|
}
|
|
|
|
ndev->stats.rx_bytes += *len;
|
|
ndev->stats.rx_packets++;
|
|
out:
|
|
return ret;
|
|
drop:
|
|
page_pool_recycle_direct(cpsw->page_pool[ch], page);
|
|
return ret;
|
|
}
|