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The TI AM65x/J721E SoCs Gigabit Ethernet Switch subsystem (CPSW2G NUSS) has two ports - One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0) and with ALE in between. It also contains - Management Data Input/Output (MDIO) interface for physical layer device (PHY) management; - Updated Address Lookup Engine (ALE) module; - (TBD) New version of Common platform time sync (CPTS) module. On the TI am65x/J721E SoCs CPSW NUSS Ethernet subsystem into device MCU domain named MCU_CPSW0. Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and one RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Introduced driver provides standard Linux net_device to user space and supports: - ifconfig up/down - MAC address configuration - ethtool operation: --driver --change --register-dump --negotiate phy --statistics --set-eee phy --show-ring --show-channels --set-channels - net_device ioctl mii-control - promisc mode - rx checksum offload for non-fragmented IPv4/IPv6 TCP/UDP packets. The CPSW NUSS can verify IPv4/IPv6 TCP/UDP packets checksum and fills csum information for each packet in psdata[2] word: - BIT(16) CHECKSUM_ERROR - indicates csum error - BIT(17) FRAGMENT - indicates fragmented packet - BIT(18) TCP_UDP_N - Indicates TCP packet was detected - BIT(19) IPV6_VALID, BIT(20) IPV4_VALID - indicates IPv6/IPv4 packet - BIT(15, 0) CHECKSUM_ADD - This is the value that was summed during the checksum computation. This value is FFFFh for non fragmented IPV4/6 UDP/TCP packets with no checksum error. RX csum offload can be disabled: ethtool -K <dev> rx-checksum on|off - tx checksum offload support for IPv4/IPv6 TCP/UDP packets (J721E only). TX csum HW offload can be enabled/disabled: ethtool -K <dev> tx-checksum-ip-generic on|off - multiq and switch between round robin/prio modes for cppi tx queues by using Netdev private flag "p0-rx-ptype-rrobin" to switch between Round Robin and Fixed priority modes: # ethtool --show-priv-flags eth0 Private flags for eth0: p0-rx-ptype-rrobin: on # ethtool --set-priv-flags eth0 p0-rx-ptype-rrobin off Number of TX DMA channels can be changed using "ethtool -L eth0 tx <N>". - GRO support: the napi_gro_receive() and napi_complete_done() are used. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
30 lines
1,017 B
C
30 lines
1,017 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* TI K3 CPPI5 descriptors pool
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*
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* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
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*/
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#ifndef K3_CPPI_DESC_POOL_H_
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#define K3_CPPI_DESC_POOL_H_
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#include <linux/device.h>
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#include <linux/types.h>
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struct k3_cppi_desc_pool;
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void k3_cppi_desc_pool_destroy(struct k3_cppi_desc_pool *pool);
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struct k3_cppi_desc_pool *
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k3_cppi_desc_pool_create_name(struct device *dev, size_t size,
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size_t desc_size,
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const char *name);
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#define k3_cppi_desc_pool_create(dev, size, desc_size) \
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k3_cppi_desc_pool_create_name(dev, size, desc_size, NULL)
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dma_addr_t
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k3_cppi_desc_pool_virt2dma(struct k3_cppi_desc_pool *pool, void *addr);
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void *
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k3_cppi_desc_pool_dma2virt(struct k3_cppi_desc_pool *pool, dma_addr_t dma);
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void *k3_cppi_desc_pool_alloc(struct k3_cppi_desc_pool *pool);
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void k3_cppi_desc_pool_free(struct k3_cppi_desc_pool *pool, void *addr);
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size_t k3_cppi_desc_pool_avail(struct k3_cppi_desc_pool *pool);
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#endif /* K3_CPPI_DESC_POOL_H_ */
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