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dbab63561b
Use a new struct array to define the asic information which asic type needs to be fixed. Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
76 lines
2.3 KiB
C
76 lines
2.3 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMD_ASIC_TYPE_H__
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#define __AMD_ASIC_TYPE_H__
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/*
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* Supported ASIC types
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*/
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enum amd_asic_type {
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CHIP_TAHITI = 0,
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CHIP_PITCAIRN, /* 1 */
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CHIP_VERDE, /* 2 */
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CHIP_OLAND, /* 3 */
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CHIP_HAINAN, /* 4 */
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CHIP_BONAIRE, /* 5 */
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CHIP_KAVERI, /* 6 */
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CHIP_KABINI, /* 7 */
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CHIP_HAWAII, /* 8 */
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CHIP_MULLINS, /* 9 */
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CHIP_TOPAZ, /* 10 */
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CHIP_TONGA, /* 11 */
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CHIP_FIJI, /* 12 */
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CHIP_CARRIZO, /* 13 */
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CHIP_STONEY, /* 14 */
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CHIP_POLARIS10, /* 15 */
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CHIP_POLARIS11, /* 16 */
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CHIP_POLARIS12, /* 17 */
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CHIP_VEGAM, /* 18 */
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CHIP_VEGA10, /* 19 */
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CHIP_VEGA12, /* 20 */
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CHIP_VEGA20, /* 21 */
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CHIP_RAVEN, /* 22 */
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CHIP_ARCTURUS, /* 23 */
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CHIP_RENOIR, /* 24 */
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CHIP_ALDEBARAN, /* 25 */
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CHIP_NAVI10, /* 26 */
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CHIP_CYAN_SKILLFISH, /* 27 */
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CHIP_NAVI14, /* 28 */
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CHIP_NAVI12, /* 29 */
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CHIP_SIENNA_CICHLID, /* 30 */
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CHIP_NAVY_FLOUNDER, /* 31 */
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CHIP_VANGOGH, /* 32 */
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CHIP_DIMGREY_CAVEFISH, /* 33 */
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CHIP_BEIGE_GOBY, /* 34 */
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CHIP_YELLOW_CARP, /* 35 */
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CHIP_IP_DISCOVERY, /* 36 */
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CHIP_LAST,
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};
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extern const char *amdgpu_asic_name[];
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struct amdgpu_asic_type_quirk {
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unsigned short device; /* PCI device ID */
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u8 revision; /* revision ID */
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unsigned short type; /* real ASIC type */
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};
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#endif /*__AMD_ASIC_TYPE_H__ */
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