Conor Dooley 0dec364ffe riscv: dts: microchip: use an mpfs specific l2 compatible ... PolarFire SoC does not have the same l2 cache controller as the fu540, featuring an extra interrupt. Appease the devicetree checker overlords by adding a PolarFire SoC specific compatible to fix the below sort of warnings: mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 34fc9cc3ae ("riscv: dts: microchip: correct L2 cache interrupts") Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2022-08-31 16:57:51 +01:00
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dts	riscv: dts: microchip: use an mpfs specific l2 compatible	2022-08-31 16:57:51 +01:00
.gitignore	RISC-V: ignore xipImage	2022-05-24 17:52:37 -07:00
install.sh	kbuild: factor out the common installation code into scripts/install.sh	2022-05-11 21:45:53 +09:00
loader.lds.S	riscv: Move kernel mapping outside of linear mapping	2021-04-26 08:25:04 -07:00
loader.S	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00
Makefile	riscv: move the (z)install rules to arch/riscv/Makefile	2021-09-10 23:08:26 -07:00