Palmer Dabbelt 8f7e001e03 RISC-V: Clean up the Zicbom block size probing ... This fixes two issues: I truncated the warning's hart ID when porting to the 64-bit hart ID code, and the original code's warning handling could fire on an uninitialized hart ID. The biggest change here is that riscv_cbom_block_size is no longer initialized, as IMO the default isn't sane: there's nothing in the ISA that mandates any specific cache block size, so falling back to one will just silently produce the wrong answer on some systems. This also changes the probing order so the cache block size is known before enabling Zicbom support. CC: stable@vger.kernel.org CC: Andrew Jones <ajones@ventanamicro.com> CC: Heiko Stuebner <heiko@sntech.de> CC: Atish Patra <atishp@rivosinc.com> Fixes: 3aefb2ee5b ("riscv: implement Zicbom-based CMO instructions + the t-head variant") Fixes: 1631ba1259 ("riscv: Add support for non-coherent devices using zicbom extension") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [Conor: fixed the redefinition errors] Tested-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220912224800.998121-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-09-13 02:06:11 -07:00
..
sifive	riscv: don't warn for sifive erratas in modules	2022-07-07 23:09:16 -07:00
thead	RISC-V: Clean up the Zicbom block size probing	2022-09-13 02:06:11 -07:00
Makefile	riscv: add memory-type errata for T-Head	2022-05-11 21:36:33 -07:00