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![Lucas Stach](/assets/img/avatar_default.png)
With the SoC matching changed to a platform driver the match data
is available only after other drivers, which may rely on it are
already probed. This breaks at least the CAAM driver on i.MX8M.
Revert the change until all those drivers have been audited and
changed to be able to eal with match data being available later
in the boot process.
Fixes: 7d981405d0
("soc: imx8m: change to use platform driver")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
233 lines
5 KiB
C
233 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <linux/platform_device.h>
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#include <linux/arm-smccc.h>
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#include <linux/of.h>
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#define REV_B1 0x21
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#define IMX8MQ_SW_INFO_B1 0x40
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#define IMX8MQ_SW_MAGIC_B1 0xff0055aa
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#define IMX_SIP_GET_SOC_INFO 0xc2000006
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#define OCOTP_UID_LOW 0x410
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#define OCOTP_UID_HIGH 0x420
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#define IMX8MP_OCOTP_UID_OFFSET 0x10
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/* Same as ANADIG_DIGPROG_IMX7D */
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#define ANADIG_DIGPROG_IMX8MM 0x800
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struct imx8_soc_data {
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char *name;
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u32 (*soc_revision)(void);
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};
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static u64 soc_uid;
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#ifdef CONFIG_HAVE_ARM_SMCCC
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static u32 imx8mq_soc_revision_from_atf(void)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(IMX_SIP_GET_SOC_INFO, 0, 0, 0, 0, 0, 0, 0, &res);
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if (res.a0 == SMCCC_RET_NOT_SUPPORTED)
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return 0;
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else
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return res.a0 & 0xff;
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}
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#else
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static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; };
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#endif
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static u32 __init imx8mq_soc_revision(void)
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{
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struct device_node *np;
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void __iomem *ocotp_base;
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u32 magic;
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u32 rev;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
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if (!np)
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return 0;
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ocotp_base = of_iomap(np, 0);
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WARN_ON(!ocotp_base);
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/*
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* SOC revision on older imx8mq is not available in fuses so query
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* the value from ATF instead.
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*/
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rev = imx8mq_soc_revision_from_atf();
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if (!rev) {
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magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1);
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if (magic == IMX8MQ_SW_MAGIC_B1)
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rev = REV_B1;
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}
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soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH);
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soc_uid <<= 32;
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soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);
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iounmap(ocotp_base);
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of_node_put(np);
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return rev;
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}
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static void __init imx8mm_soc_uid(void)
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{
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void __iomem *ocotp_base;
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struct device_node *np;
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u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
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IMX8MP_OCOTP_UID_OFFSET : 0;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp");
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if (!np)
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return;
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ocotp_base = of_iomap(np, 0);
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WARN_ON(!ocotp_base);
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soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
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soc_uid <<= 32;
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soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
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iounmap(ocotp_base);
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of_node_put(np);
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}
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static u32 __init imx8mm_soc_revision(void)
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{
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struct device_node *np;
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void __iomem *anatop_base;
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u32 rev;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
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if (!np)
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return 0;
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anatop_base = of_iomap(np, 0);
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WARN_ON(!anatop_base);
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rev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM);
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iounmap(anatop_base);
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of_node_put(np);
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imx8mm_soc_uid();
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return rev;
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}
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static const struct imx8_soc_data imx8mq_soc_data = {
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.name = "i.MX8MQ",
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.soc_revision = imx8mq_soc_revision,
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};
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static const struct imx8_soc_data imx8mm_soc_data = {
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.name = "i.MX8MM",
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.soc_revision = imx8mm_soc_revision,
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};
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static const struct imx8_soc_data imx8mn_soc_data = {
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.name = "i.MX8MN",
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.soc_revision = imx8mm_soc_revision,
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};
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static const struct imx8_soc_data imx8mp_soc_data = {
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.name = "i.MX8MP",
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.soc_revision = imx8mm_soc_revision,
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};
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static __maybe_unused const struct of_device_id imx8_soc_match[] = {
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{ .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
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{ .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },
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{ .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },
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{ .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, },
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{ }
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};
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#define imx8_revision(soc_rev) \
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soc_rev ? \
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kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf, soc_rev & 0xf) : \
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"unknown"
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static int __init imx8_soc_init(void)
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{
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struct soc_device_attribute *soc_dev_attr;
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struct soc_device *soc_dev;
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const struct of_device_id *id;
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u32 soc_rev = 0;
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const struct imx8_soc_data *data;
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int ret;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return -ENOMEM;
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soc_dev_attr->family = "Freescale i.MX";
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ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine);
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if (ret)
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goto free_soc;
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id = of_match_node(imx8_soc_match, of_root);
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if (!id) {
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ret = -ENODEV;
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goto free_soc;
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}
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data = id->data;
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if (data) {
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soc_dev_attr->soc_id = data->name;
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if (data->soc_revision)
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soc_rev = data->soc_revision();
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}
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soc_dev_attr->revision = imx8_revision(soc_rev);
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if (!soc_dev_attr->revision) {
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ret = -ENOMEM;
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goto free_soc;
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}
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soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
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if (!soc_dev_attr->serial_number) {
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ret = -ENOMEM;
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goto free_rev;
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}
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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ret = PTR_ERR(soc_dev);
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goto free_serial_number;
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}
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pr_info("SoC: %s revision %s\n", soc_dev_attr->soc_id,
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soc_dev_attr->revision);
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if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
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platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
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return 0;
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free_serial_number:
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kfree(soc_dev_attr->serial_number);
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free_rev:
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if (strcmp(soc_dev_attr->revision, "unknown"))
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kfree(soc_dev_attr->revision);
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free_soc:
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kfree(soc_dev_attr);
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return ret;
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}
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device_initcall(imx8_soc_init);
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