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![Linus Walleij](/assets/img/avatar_default.png)
The kernel test robot found this inconsistency: drivers/soc/ixp4xx/ixp4xx-npe.c:737:34: warning: 'ixp4xx_npe_of_match' defined but not used [-Wunused-const-variable=] 737 | static const struct of_device_id ixp4xx_npe_of_match[] = { This is because the match is enclosed in the of_match_ptr() which compiles into NULL when OF is disabled and this is unnecessary. Fix it by dropping of_match_ptr() around the match. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220626074315.61209-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
781 lines
22 KiB
C
781 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel IXP4xx Network Processor Engine driver for Linux
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*
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* Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
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*
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* The code is based on publicly available information:
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* - Intel IXP4xx Developer's Manual and other e-papers
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* - Intel IXP400 Access Library Software (BSD license)
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* - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
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* Thanks, Christian.
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/soc/ixp4xx/npe.h>
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#include <linux/soc/ixp4xx/cpu.h>
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#define DEBUG_MSG 0
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#define DEBUG_FW 0
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#define NPE_COUNT 3
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#define MAX_RETRIES 1000 /* microseconds */
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#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
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#define NPE_46X_DATA_SIZE 0x1000
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#define NPE_A_42X_INSTR_SIZE 0x1000
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#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
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#define NPE_46X_INSTR_SIZE 0x1000
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#define REGS_SIZE 0x1000
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#define NPE_PHYS_REG 32
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#define FW_MAGIC 0xFEEDF00D
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#define FW_BLOCK_TYPE_INSTR 0x0
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#define FW_BLOCK_TYPE_DATA 0x1
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#define FW_BLOCK_TYPE_EOF 0xF
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/* NPE exec status (read) and command (write) */
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#define CMD_NPE_STEP 0x01
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#define CMD_NPE_START 0x02
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#define CMD_NPE_STOP 0x03
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#define CMD_NPE_CLR_PIPE 0x04
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#define CMD_CLR_PROFILE_CNT 0x0C
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#define CMD_RD_INS_MEM 0x10 /* instruction memory */
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#define CMD_WR_INS_MEM 0x11
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#define CMD_RD_DATA_MEM 0x12 /* data memory */
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#define CMD_WR_DATA_MEM 0x13
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#define CMD_RD_ECS_REG 0x14 /* exec access register */
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#define CMD_WR_ECS_REG 0x15
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#define STAT_RUN 0x80000000
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#define STAT_STOP 0x40000000
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#define STAT_CLEAR 0x20000000
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#define STAT_ECS_K 0x00800000 /* pipeline clean */
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#define NPE_STEVT 0x1B
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#define NPE_STARTPC 0x1C
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#define NPE_REGMAP 0x1E
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#define NPE_CINDEX 0x1F
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#define INSTR_WR_REG_SHORT 0x0000C000
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#define INSTR_WR_REG_BYTE 0x00004000
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#define INSTR_RD_FIFO 0x0F888220
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#define INSTR_RESET_MBOX 0x0FAC8210
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#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
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#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
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#define ECS_BG_CTXT_REG_2 0x02
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#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
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#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
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#define ECS_PRI_1_CTXT_REG_2 0x06
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#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
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#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
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#define ECS_PRI_2_CTXT_REG_2 0x0A
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#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
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#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
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#define ECS_DBG_CTXT_REG_2 0x0E
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#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
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#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
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#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
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#define ECS_REG_0_LDUR_BITS 8
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#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
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#define ECS_REG_1_CCTXT_BITS 16
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#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
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#define ECS_REG_1_SELCTXT_BITS 0
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#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
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#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
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#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
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/* NPE watchpoint_fifo register bit */
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#define WFIFO_VALID 0x80000000
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/* NPE messaging_status register bit definitions */
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#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
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#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
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#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
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#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
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#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
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#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
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#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
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#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
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/* NPE messaging_control register bit definitions */
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#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
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#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
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#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
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#define MSGCTL_IN_FIFO_WRITE 0x02000000
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/* NPE mailbox_status value for reset */
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#define RESET_MBOX_STAT 0x0000F0F0
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#define NPE_A_FIRMWARE "NPE-A"
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#define NPE_B_FIRMWARE "NPE-B"
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#define NPE_C_FIRMWARE "NPE-C"
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const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE };
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#define print_npe(pri, npe, fmt, ...) \
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printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
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#if DEBUG_MSG
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#define debug_msg(npe, fmt, ...) \
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print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
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#else
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#define debug_msg(npe, fmt, ...)
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#endif
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static struct {
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u32 reg, val;
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} ecs_reset[] = {
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{ ECS_BG_CTXT_REG_0, 0xA0000000 },
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{ ECS_BG_CTXT_REG_1, 0x01000000 },
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{ ECS_BG_CTXT_REG_2, 0x00008000 },
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{ ECS_PRI_1_CTXT_REG_0, 0x20000080 },
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{ ECS_PRI_1_CTXT_REG_1, 0x01000000 },
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{ ECS_PRI_1_CTXT_REG_2, 0x00008000 },
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{ ECS_PRI_2_CTXT_REG_0, 0x20000080 },
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{ ECS_PRI_2_CTXT_REG_1, 0x01000000 },
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{ ECS_PRI_2_CTXT_REG_2, 0x00008000 },
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{ ECS_DBG_CTXT_REG_0, 0x20000000 },
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{ ECS_DBG_CTXT_REG_1, 0x00000000 },
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{ ECS_DBG_CTXT_REG_2, 0x001E0000 },
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{ ECS_INSTRUCT_REG, 0x1003C00F },
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};
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static struct npe npe_tab[NPE_COUNT] = {
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{
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.id = 0,
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}, {
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.id = 1,
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}, {
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.id = 2,
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}
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};
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int npe_running(struct npe *npe)
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{
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return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
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}
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static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
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{
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__raw_writel(data, &npe->regs->exec_data);
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__raw_writel(addr, &npe->regs->exec_addr);
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__raw_writel(cmd, &npe->regs->exec_status_cmd);
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}
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static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
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{
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__raw_writel(addr, &npe->regs->exec_addr);
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__raw_writel(cmd, &npe->regs->exec_status_cmd);
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/* Iintroduce extra read cycles after issuing read command to NPE
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so that we read the register after the NPE has updated it.
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This is to overcome race condition between XScale and NPE */
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__raw_readl(&npe->regs->exec_data);
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__raw_readl(&npe->regs->exec_data);
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return __raw_readl(&npe->regs->exec_data);
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}
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static void npe_clear_active(struct npe *npe, u32 reg)
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{
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u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
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npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
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}
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static void npe_start(struct npe *npe)
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{
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/* ensure only Background Context Stack Level is active */
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npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
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npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
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npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
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__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
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__raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
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}
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static void npe_stop(struct npe *npe)
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{
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__raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
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__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
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}
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static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
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u32 ldur)
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{
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u32 wc;
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int i;
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/* set the Active bit, and the LDUR, in the debug level */
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npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
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ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
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/* set CCTXT at ECS DEBUG L3 to specify in which context to execute
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the instruction, and set SELCTXT at ECS DEBUG Level to specify
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which context store to access.
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Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
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*/
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npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
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(ctx << ECS_REG_1_CCTXT_BITS) |
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(ctx << ECS_REG_1_SELCTXT_BITS));
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/* clear the pipeline */
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__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
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/* load NPE instruction into the instruction register */
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npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
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/* we need this value later to wait for completion of NPE execution
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step */
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wc = __raw_readl(&npe->regs->watch_count);
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/* issue a Step One command via the Execution Control register */
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__raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
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/* Watch Count register increments when NPE completes an instruction */
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for (i = 0; i < MAX_RETRIES; i++) {
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if (wc != __raw_readl(&npe->regs->watch_count))
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return 0;
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udelay(1);
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}
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print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
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return -ETIMEDOUT;
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}
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static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
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u8 val, u32 ctx)
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{
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/* here we build the NPE assembler instruction: mov8 d0, #0 */
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u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
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addr << 9 | /* base Operand */
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(val & 0x1F) << 4 | /* lower 5 bits to immediate data */
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(val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
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return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
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}
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static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
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u16 val, u32 ctx)
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{
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/* here we build the NPE assembler instruction: mov16 d0, #0 */
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u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
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addr << 9 | /* base Operand */
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(val & 0x1F) << 4 | /* lower 5 bits to immediate data */
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(val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
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return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
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}
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static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
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u32 val, u32 ctx)
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{
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/* write in 16 bit steps first the high and then the low value */
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if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
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return -ETIMEDOUT;
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return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
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}
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static int npe_reset(struct npe *npe)
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{
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u32 reset_bit = (IXP4XX_FEATURE_RESET_NPEA << npe->id);
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u32 val, ctl, exec_count, ctx_reg2;
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int i;
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ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
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0x3F3FFFFF;
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/* disable parity interrupt */
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__raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
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/* pre exec - debug instruction */
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/* turn off the halt bit by clearing Execution Count register. */
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exec_count = __raw_readl(&npe->regs->exec_count);
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__raw_writel(0, &npe->regs->exec_count);
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/* ensure that IF and IE are on (temporarily), so that we don't end up
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stepping forever */
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ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
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npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
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ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
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/* clear the FIFOs */
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while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
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;
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while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
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/* read from the outFIFO until empty */
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print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
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__raw_readl(&npe->regs->in_out_fifo));
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while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
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/* step execution of the NPE intruction to read inFIFO using
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the Debug Executing Context stack */
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if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
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return -ETIMEDOUT;
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/* reset the mailbox reg from the XScale side */
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__raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
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/* from NPE side */
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if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
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return -ETIMEDOUT;
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/* Reset the physical registers in the NPE register file */
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for (val = 0; val < NPE_PHYS_REG; val++) {
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if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
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return -ETIMEDOUT;
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/* address is either 0 or 4 */
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if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
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return -ETIMEDOUT;
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}
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/* Reset the context store = each context's Context Store registers */
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/* Context 0 has no STARTPC. Instead, this value is used to set NextPC
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for Background ECS, to set where NPE starts executing code */
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val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
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val &= ~ECS_REG_0_NEXTPC_MASK;
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val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
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npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
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for (i = 0; i < 16; i++) {
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if (i) { /* Context 0 has no STEVT nor STARTPC */
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/* STEVT = off, 0x80 */
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if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
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return -ETIMEDOUT;
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if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
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return -ETIMEDOUT;
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}
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/* REGMAP = d0->p0, d8->p2, d16->p4 */
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if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
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return -ETIMEDOUT;
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if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
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return -ETIMEDOUT;
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}
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/* post exec */
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/* clear active bit in debug level */
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npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
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/* clear the pipeline */
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__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
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/* restore previous values */
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__raw_writel(exec_count, &npe->regs->exec_count);
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npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
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/* write reset values to Execution Context Stack registers */
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for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
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npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
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ecs_reset[val].val);
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/* clear the profile counter */
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__raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
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__raw_writel(0, &npe->regs->exec_count);
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__raw_writel(0, &npe->regs->action_points[0]);
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__raw_writel(0, &npe->regs->action_points[1]);
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__raw_writel(0, &npe->regs->action_points[2]);
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__raw_writel(0, &npe->regs->action_points[3]);
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__raw_writel(0, &npe->regs->watch_count);
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/*
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* We need to work on cached values here because the register
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* will read inverted but needs to be written non-inverted.
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|
*/
|
|
val = cpu_ixp4xx_features(npe->rmap);
|
|
/* reset the NPE */
|
|
regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val & ~reset_bit);
|
|
/* deassert reset */
|
|
regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val | reset_bit);
|
|
|
|
for (i = 0; i < MAX_RETRIES; i++) {
|
|
val = cpu_ixp4xx_features(npe->rmap);
|
|
if (val & reset_bit)
|
|
break; /* NPE is back alive */
|
|
udelay(1);
|
|
}
|
|
if (i == MAX_RETRIES)
|
|
return -ETIMEDOUT;
|
|
|
|
npe_stop(npe);
|
|
|
|
/* restore NPE configuration bus Control Register - parity settings */
|
|
__raw_writel(ctl, &npe->regs->messaging_control);
|
|
return 0;
|
|
}
|
|
|
|
|
|
int npe_send_message(struct npe *npe, const void *msg, const char *what)
|
|
{
|
|
const u32 *send = msg;
|
|
int cycles = 0;
|
|
|
|
debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
|
|
what, send[0], send[1]);
|
|
|
|
if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
|
|
debug_msg(npe, "NPE input FIFO not empty\n");
|
|
return -EIO;
|
|
}
|
|
|
|
__raw_writel(send[0], &npe->regs->in_out_fifo);
|
|
|
|
if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
|
|
debug_msg(npe, "NPE input FIFO full\n");
|
|
return -EIO;
|
|
}
|
|
|
|
__raw_writel(send[1], &npe->regs->in_out_fifo);
|
|
|
|
while ((cycles < MAX_RETRIES) &&
|
|
(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
|
|
udelay(1);
|
|
cycles++;
|
|
}
|
|
|
|
if (cycles == MAX_RETRIES) {
|
|
debug_msg(npe, "Timeout sending message\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
#if DEBUG_MSG > 1
|
|
debug_msg(npe, "Sending a message took %i cycles\n", cycles);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int npe_recv_message(struct npe *npe, void *msg, const char *what)
|
|
{
|
|
u32 *recv = msg;
|
|
int cycles = 0, cnt = 0;
|
|
|
|
debug_msg(npe, "Trying to receive message %s\n", what);
|
|
|
|
while (cycles < MAX_RETRIES) {
|
|
if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
|
|
recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
|
|
if (cnt == 2)
|
|
break;
|
|
} else {
|
|
udelay(1);
|
|
cycles++;
|
|
}
|
|
}
|
|
|
|
switch(cnt) {
|
|
case 1:
|
|
debug_msg(npe, "Received [%08X]\n", recv[0]);
|
|
break;
|
|
case 2:
|
|
debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
|
|
break;
|
|
}
|
|
|
|
if (cycles == MAX_RETRIES) {
|
|
debug_msg(npe, "Timeout waiting for message\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
#if DEBUG_MSG > 1
|
|
debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
|
|
{
|
|
int result;
|
|
u32 *send = msg, recv[2];
|
|
|
|
if ((result = npe_send_message(npe, msg, what)) != 0)
|
|
return result;
|
|
if ((result = npe_recv_message(npe, recv, what)) != 0)
|
|
return result;
|
|
|
|
if ((recv[0] != send[0]) || (recv[1] != send[1])) {
|
|
debug_msg(npe, "Message %s: unexpected message received\n",
|
|
what);
|
|
return -EIO;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
|
|
{
|
|
const struct firmware *fw_entry;
|
|
|
|
struct dl_block {
|
|
u32 type;
|
|
u32 offset;
|
|
} *blk;
|
|
|
|
struct dl_image {
|
|
u32 magic;
|
|
u32 id;
|
|
u32 size;
|
|
union {
|
|
u32 data[0];
|
|
struct dl_block blocks[0];
|
|
};
|
|
} *image;
|
|
|
|
struct dl_codeblock {
|
|
u32 npe_addr;
|
|
u32 size;
|
|
u32 data[0];
|
|
} *cb;
|
|
|
|
int i, j, err, data_size, instr_size, blocks, table_end;
|
|
u32 cmd;
|
|
|
|
if ((err = request_firmware(&fw_entry, name, dev)) != 0)
|
|
return err;
|
|
|
|
err = -EINVAL;
|
|
if (fw_entry->size < sizeof(struct dl_image)) {
|
|
print_npe(KERN_ERR, npe, "incomplete firmware file\n");
|
|
goto err;
|
|
}
|
|
image = (struct dl_image*)fw_entry->data;
|
|
|
|
#if DEBUG_FW
|
|
print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
|
|
image->magic, image->id, image->size, image->size * 4);
|
|
#endif
|
|
|
|
if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
|
|
image->id = swab32(image->id);
|
|
image->size = swab32(image->size);
|
|
} else if (image->magic != FW_MAGIC) {
|
|
print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
|
|
image->magic);
|
|
goto err;
|
|
}
|
|
if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
|
|
print_npe(KERN_ERR, npe,
|
|
"inconsistent size of firmware file\n");
|
|
goto err;
|
|
}
|
|
if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
|
|
print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
|
|
goto err;
|
|
}
|
|
if (image->magic == swab32(FW_MAGIC))
|
|
for (i = 0; i < image->size; i++)
|
|
image->data[i] = swab32(image->data[i]);
|
|
|
|
if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
|
|
print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on "
|
|
"IXP42x\n");
|
|
goto err;
|
|
}
|
|
|
|
if (npe_running(npe)) {
|
|
print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
|
|
"already running\n");
|
|
err = -EBUSY;
|
|
goto err;
|
|
}
|
|
#if 0
|
|
npe_stop(npe);
|
|
npe_reset(npe);
|
|
#endif
|
|
|
|
print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
|
|
"revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
|
|
(image->id >> 8) & 0xFF, image->id & 0xFF);
|
|
|
|
if (cpu_is_ixp42x()) {
|
|
if (!npe->id)
|
|
instr_size = NPE_A_42X_INSTR_SIZE;
|
|
else
|
|
instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
|
|
data_size = NPE_42X_DATA_SIZE;
|
|
} else {
|
|
instr_size = NPE_46X_INSTR_SIZE;
|
|
data_size = NPE_46X_DATA_SIZE;
|
|
}
|
|
|
|
for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
|
|
blocks++)
|
|
if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
|
|
break;
|
|
if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
|
|
print_npe(KERN_INFO, npe, "firmware EOF block marker not "
|
|
"found\n");
|
|
goto err;
|
|
}
|
|
|
|
#if DEBUG_FW
|
|
print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
|
|
#endif
|
|
|
|
table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
|
|
for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
|
|
if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
|
|
|| blk->offset < table_end) {
|
|
print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
|
|
"firmware block #%i\n", blk->offset, i);
|
|
goto err;
|
|
}
|
|
|
|
cb = (struct dl_codeblock*)&image->data[blk->offset];
|
|
if (blk->type == FW_BLOCK_TYPE_INSTR) {
|
|
if (cb->npe_addr + cb->size > instr_size)
|
|
goto too_big;
|
|
cmd = CMD_WR_INS_MEM;
|
|
} else if (blk->type == FW_BLOCK_TYPE_DATA) {
|
|
if (cb->npe_addr + cb->size > data_size)
|
|
goto too_big;
|
|
cmd = CMD_WR_DATA_MEM;
|
|
} else {
|
|
print_npe(KERN_INFO, npe, "invalid firmware block #%i "
|
|
"type 0x%X\n", i, blk->type);
|
|
goto err;
|
|
}
|
|
if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
|
|
print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
|
|
"fit in firmware image: type %c, start 0x%X,"
|
|
" length 0x%X\n", i,
|
|
blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
|
|
cb->npe_addr, cb->size);
|
|
goto err;
|
|
}
|
|
|
|
for (j = 0; j < cb->size; j++)
|
|
npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
|
|
}
|
|
|
|
npe_start(npe);
|
|
if (!npe_running(npe))
|
|
print_npe(KERN_ERR, npe, "unable to start\n");
|
|
release_firmware(fw_entry);
|
|
return 0;
|
|
|
|
too_big:
|
|
print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
|
|
"memory: type %c, start 0x%X, length 0x%X\n", i,
|
|
blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
|
|
cb->npe_addr, cb->size);
|
|
err:
|
|
release_firmware(fw_entry);
|
|
return err;
|
|
}
|
|
|
|
|
|
struct npe *npe_request(unsigned id)
|
|
{
|
|
if (id < NPE_COUNT)
|
|
if (npe_tab[id].valid)
|
|
if (try_module_get(THIS_MODULE))
|
|
return &npe_tab[id];
|
|
return NULL;
|
|
}
|
|
|
|
void npe_release(struct npe *npe)
|
|
{
|
|
module_put(THIS_MODULE);
|
|
}
|
|
|
|
static int ixp4xx_npe_probe(struct platform_device *pdev)
|
|
{
|
|
int i, found = 0;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
struct resource *res;
|
|
struct regmap *rmap;
|
|
u32 val;
|
|
|
|
/* This system has only one syscon, so fetch it */
|
|
rmap = syscon_regmap_lookup_by_compatible("syscon");
|
|
if (IS_ERR(rmap))
|
|
return dev_err_probe(dev, PTR_ERR(rmap),
|
|
"failed to look up syscon\n");
|
|
|
|
for (i = 0; i < NPE_COUNT; i++) {
|
|
struct npe *npe = &npe_tab[i];
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
|
if (!res)
|
|
return -ENODEV;
|
|
|
|
val = cpu_ixp4xx_features(rmap);
|
|
|
|
if (!(val & (IXP4XX_FEATURE_RESET_NPEA << i))) {
|
|
dev_info(dev, "NPE%d at %pR not available\n",
|
|
i, res);
|
|
continue; /* NPE already disabled or not present */
|
|
}
|
|
npe->regs = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(npe->regs))
|
|
return PTR_ERR(npe->regs);
|
|
npe->rmap = rmap;
|
|
|
|
if (npe_reset(npe)) {
|
|
dev_info(dev, "NPE%d at %pR does not reset\n",
|
|
i, res);
|
|
continue;
|
|
}
|
|
npe->valid = 1;
|
|
dev_info(dev, "NPE%d at %pR registered\n", i, res);
|
|
found++;
|
|
}
|
|
|
|
if (!found)
|
|
return -ENODEV;
|
|
|
|
/* Spawn crypto subdevice if using device tree */
|
|
if (IS_ENABLED(CONFIG_OF) && np)
|
|
devm_of_platform_populate(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ixp4xx_npe_remove(struct platform_device *pdev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < NPE_COUNT; i++)
|
|
if (npe_tab[i].regs) {
|
|
npe_reset(&npe_tab[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id ixp4xx_npe_of_match[] = {
|
|
{
|
|
.compatible = "intel,ixp4xx-network-processing-engine",
|
|
},
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver ixp4xx_npe_driver = {
|
|
.driver = {
|
|
.name = "ixp4xx-npe",
|
|
.of_match_table = ixp4xx_npe_of_match,
|
|
},
|
|
.probe = ixp4xx_npe_probe,
|
|
.remove = ixp4xx_npe_remove,
|
|
};
|
|
module_platform_driver(ixp4xx_npe_driver);
|
|
|
|
MODULE_AUTHOR("Krzysztof Halasa");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_FIRMWARE(NPE_A_FIRMWARE);
|
|
MODULE_FIRMWARE(NPE_B_FIRMWARE);
|
|
MODULE_FIRMWARE(NPE_C_FIRMWARE);
|
|
|
|
EXPORT_SYMBOL(npe_names);
|
|
EXPORT_SYMBOL(npe_running);
|
|
EXPORT_SYMBOL(npe_request);
|
|
EXPORT_SYMBOL(npe_release);
|
|
EXPORT_SYMBOL(npe_load_firmware);
|
|
EXPORT_SYMBOL(npe_send_message);
|
|
EXPORT_SYMBOL(npe_recv_message);
|
|
EXPORT_SYMBOL(npe_send_recv_message);
|