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![Yash Shah](/assets/img/avatar_default.png)
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the L2 cache controller driver to support this additional interrupt in case of FU740-C000 chip. Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
237 lines
6.2 KiB
C
237 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* SiFive L2 cache controller Driver
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*
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* Copyright (C) 2018-2019 SiFive, Inc.
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*
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*/
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#include <linux/debugfs.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/device.h>
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#include <asm/cacheinfo.h>
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#include <soc/sifive/sifive_l2_cache.h>
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#define SIFIVE_L2_DIRECCFIX_LOW 0x100
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#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
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#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
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#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
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#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
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#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
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#define SIFIVE_L2_DATECCFIX_LOW 0x140
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#define SIFIVE_L2_DATECCFIX_HIGH 0x144
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#define SIFIVE_L2_DATECCFIX_COUNT 0x148
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#define SIFIVE_L2_DATECCFAIL_LOW 0x160
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#define SIFIVE_L2_DATECCFAIL_HIGH 0x164
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#define SIFIVE_L2_DATECCFAIL_COUNT 0x168
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#define SIFIVE_L2_CONFIG 0x00
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#define SIFIVE_L2_WAYENABLE 0x08
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#define SIFIVE_L2_ECCINJECTERR 0x40
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#define SIFIVE_L2_MAX_ECCINTR 4
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static void __iomem *l2_base;
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static int g_irq[SIFIVE_L2_MAX_ECCINTR];
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static struct riscv_cacheinfo_ops l2_cache_ops;
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enum {
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DIR_CORR = 0,
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DATA_CORR,
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DATA_UNCORR,
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DIR_UNCORR,
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};
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#ifdef CONFIG_DEBUG_FS
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static struct dentry *sifive_test;
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static ssize_t l2_write(struct file *file, const char __user *data,
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size_t count, loff_t *ppos)
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{
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unsigned int val;
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if (kstrtouint_from_user(data, count, 0, &val))
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return -EINVAL;
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if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
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writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
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else
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return -EINVAL;
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return count;
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}
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static const struct file_operations l2_fops = {
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.owner = THIS_MODULE,
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.open = simple_open,
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.write = l2_write
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};
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static void setup_sifive_debug(void)
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{
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sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
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debugfs_create_file("sifive_debug_inject_error", 0200,
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sifive_test, NULL, &l2_fops);
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}
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#endif
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static void l2_config_read(void)
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{
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u32 regval, val;
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regval = readl(l2_base + SIFIVE_L2_CONFIG);
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val = regval & 0xFF;
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pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
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val = (regval & 0xFF00) >> 8;
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pr_info("L2CACHE: No. of ways per bank: %d\n", val);
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val = (regval & 0xFF0000) >> 16;
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pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
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val = (regval & 0xFF000000) >> 24;
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pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
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regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
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pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
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}
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static const struct of_device_id sifive_l2_ids[] = {
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{ .compatible = "sifive,fu540-c000-ccache" },
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{ .compatible = "sifive,fu740-c000-ccache" },
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{ /* end of table */ },
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};
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static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
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int register_sifive_l2_error_notifier(struct notifier_block *nb)
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{
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return atomic_notifier_chain_register(&l2_err_chain, nb);
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}
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EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
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int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
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{
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return atomic_notifier_chain_unregister(&l2_err_chain, nb);
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}
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EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
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static int l2_largest_wayenabled(void)
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{
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return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
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}
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static ssize_t number_of_ways_enabled_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return sprintf(buf, "%u\n", l2_largest_wayenabled());
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}
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static DEVICE_ATTR_RO(number_of_ways_enabled);
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static struct attribute *priv_attrs[] = {
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&dev_attr_number_of_ways_enabled.attr,
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NULL,
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};
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static const struct attribute_group priv_attr_group = {
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.attrs = priv_attrs,
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};
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static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf)
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{
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/* We want to use private group for L2 cache only */
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if (this_leaf->level == 2)
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return &priv_attr_group;
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else
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return NULL;
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}
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static irqreturn_t l2_int_handler(int irq, void *device)
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{
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unsigned int add_h, add_l;
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if (irq == g_irq[DIR_CORR]) {
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add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
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add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
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pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
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/* Reading this register clears the DirError interrupt sig */
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readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
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atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
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"DirECCFix");
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}
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if (irq == g_irq[DIR_UNCORR]) {
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add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
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add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
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/* Reading this register clears the DirFail interrupt sig */
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readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
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atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
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"DirECCFail");
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panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
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}
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if (irq == g_irq[DATA_CORR]) {
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add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
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add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
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pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
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/* Reading this register clears the DataError interrupt sig */
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readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
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atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
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"DatECCFix");
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}
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if (irq == g_irq[DATA_UNCORR]) {
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add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
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add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
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pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
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/* Reading this register clears the DataFail interrupt sig */
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readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
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atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
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"DatECCFail");
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}
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return IRQ_HANDLED;
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}
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static int __init sifive_l2_init(void)
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{
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struct device_node *np;
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struct resource res;
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int i, rc, intr_num;
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np = of_find_matching_node(NULL, sifive_l2_ids);
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if (!np)
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return -ENODEV;
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if (of_address_to_resource(np, 0, &res))
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return -ENODEV;
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l2_base = ioremap(res.start, resource_size(&res));
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if (!l2_base)
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return -ENOMEM;
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intr_num = of_property_count_u32_elems(np, "interrupts");
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if (!intr_num) {
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pr_err("L2CACHE: no interrupts property\n");
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return -ENODEV;
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}
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for (i = 0; i < intr_num; i++) {
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g_irq[i] = irq_of_parse_and_map(np, i);
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rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
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if (rc) {
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pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
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return rc;
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}
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}
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l2_config_read();
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l2_cache_ops.get_priv_group = l2_get_priv_group;
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riscv_set_cacheinfo_ops(&l2_cache_ops);
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#ifdef CONFIG_DEBUG_FS
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setup_sifive_debug();
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#endif
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return 0;
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}
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device_initcall(sifive_l2_init);
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