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![Philipp Hortmann](/assets/img/avatar_default.png)
Convert once used macro to static function. Multiline macros are not liked by kernel community. Rename variable byOrgValue to reg_value to avoid CamelCase which is not accepted by checkpatch.pl. Change variable declaration to u8 as this improves readability. Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com> Link: https://lore.kernel.org/r/cbfe5cc170b68564ff45bb7f45c63de241c2a664.1658986804.git.philipp.g.hortmann@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
688 lines
21 KiB
C
688 lines
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
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* All rights reserved.
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*
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* Purpose: MAC routines
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*
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* Author: Tevin Chen
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*
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* Date: May 21, 1996
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*
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* Revision History:
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* 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
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* 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
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* 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
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*/
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#ifndef __MAC_H__
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#define __MAC_H__
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#include "device.h"
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/*--------------------- Export Definitions -------------------------*/
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/* Registers in the MAC */
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#define MAC_MAX_CONTEXT_SIZE_PAGE0 256
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#define MAC_MAX_CONTEXT_SIZE_PAGE1 128
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/* Registers not related to 802.11b */
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#define MAC_REG_BCFG0 0x00
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#define MAC_REG_BCFG1 0x01
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#define MAC_REG_FCR0 0x02
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#define MAC_REG_FCR1 0x03
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#define MAC_REG_BISTCMD 0x04
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#define MAC_REG_BISTSR0 0x05
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#define MAC_REG_BISTSR1 0x06
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#define MAC_REG_BISTSR2 0x07
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#define MAC_REG_I2MCSR 0x08
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#define MAC_REG_I2MTGID 0x09
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#define MAC_REG_I2MTGAD 0x0A
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#define MAC_REG_I2MCFG 0x0B
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#define MAC_REG_I2MDIPT 0x0C
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#define MAC_REG_I2MDOPT 0x0E
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#define MAC_REG_PMC0 0x10
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#define MAC_REG_PMC1 0x11
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#define MAC_REG_STICKHW 0x12
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#define MAC_REG_LOCALID 0x14
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#define MAC_REG_TESTCFG 0x15
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#define MAC_REG_JUMPER0 0x16
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#define MAC_REG_JUMPER1 0x17
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#define MAC_REG_TMCTL0 0x18
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#define MAC_REG_TMCTL1 0x19
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#define MAC_REG_TMDATA0 0x1C
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/* MAC Parameter related */
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#define MAC_REG_LRT 0x20
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#define MAC_REG_SRT 0x21
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#define MAC_REG_SIFS 0x22
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#define MAC_REG_DIFS 0x23
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#define MAC_REG_EIFS 0x24
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#define MAC_REG_SLOT 0x25
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#define MAC_REG_BI 0x26
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#define MAC_REG_CWMAXMIN0 0x28
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#define MAC_REG_LINKOFFTOTM 0x2A
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#define MAC_REG_SWTMOT 0x2B
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#define MAC_REG_MIBCNTR 0x2C
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#define MAC_REG_RTSOKCNT 0x2C
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#define MAC_REG_RTSFAILCNT 0x2D
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#define MAC_REG_ACKFAILCNT 0x2E
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#define MAC_REG_FCSERRCNT 0x2F
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/* TSF Related */
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#define MAC_REG_TSFCNTR 0x30
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#define MAC_REG_NEXTTBTT 0x38
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#define MAC_REG_TSFOFST 0x40
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#define MAC_REG_TFTCTL 0x48
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/* WMAC Control/Status Related */
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#define MAC_REG_ENCFG 0x4C
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#define MAC_REG_PAGE1SEL 0x4F
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#define MAC_REG_CFG 0x50
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#define MAC_REG_TEST 0x52
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#define MAC_REG_HOSTCR 0x54
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#define MAC_REG_MACCR 0x55
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#define MAC_REG_RCR 0x56
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#define MAC_REG_TCR 0x57
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#define MAC_REG_IMR 0x58
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#define MAC_REG_ISR 0x5C
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/* Power Saving Related */
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#define MAC_REG_PSCFG 0x60
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#define MAC_REG_PSCTL 0x61
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#define MAC_REG_PSPWRSIG 0x62
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#define MAC_REG_BBCR13 0x63
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#define MAC_REG_AIDATIM 0x64
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#define MAC_REG_PWBT 0x66
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#define MAC_REG_WAKEOKTMR 0x68
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#define MAC_REG_CALTMR 0x69
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#define MAC_REG_SYNSPACCNT 0x6A
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#define MAC_REG_WAKSYNOPT 0x6B
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/* Baseband/IF Control Group */
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#define MAC_REG_BBREGCTL 0x6C
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#define MAC_REG_CHANNEL 0x6D
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#define MAC_REG_BBREGADR 0x6E
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#define MAC_REG_BBREGDATA 0x6F
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#define MAC_REG_IFREGCTL 0x70
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#define MAC_REG_IFDATA 0x71
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#define MAC_REG_ITRTMSET 0x74
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#define MAC_REG_PAPEDELAY 0x77
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#define MAC_REG_SOFTPWRCTL 0x78
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#define MAC_REG_GPIOCTL0 0x7A
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#define MAC_REG_GPIOCTL1 0x7B
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/* MAC DMA Related Group */
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#define MAC_REG_TXDMACTL0 0x7C
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#define MAC_REG_TXDMAPTR0 0x80
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#define MAC_REG_AC0DMACTL 0x84
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#define MAC_REG_AC0DMAPTR 0x88
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#define MAC_REG_BCNDMACTL 0x8C
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#define MAC_REG_BCNDMAPTR 0x90
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#define MAC_REG_RXDMACTL0 0x94
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#define MAC_REG_RXDMAPTR0 0x98
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#define MAC_REG_RXDMACTL1 0x9C
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#define MAC_REG_RXDMAPTR1 0xA0
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#define MAC_REG_SYNCDMACTL 0xA4
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#define MAC_REG_SYNCDMAPTR 0xA8
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#define MAC_REG_ATIMDMACTL 0xAC
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#define MAC_REG_ATIMDMAPTR 0xB0
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/* MiscFF PIO related */
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#define MAC_REG_MISCFFNDEX 0xB4
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#define MAC_REG_MISCFFCTL 0xB6
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#define MAC_REG_MISCFFDATA 0xB8
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/* Extend SW Timer */
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#define MAC_REG_TMDATA1 0xBC
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/* WOW Related Group */
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#define MAC_REG_WAKEUPEN0 0xC0
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#define MAC_REG_WAKEUPEN1 0xC1
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#define MAC_REG_WAKEUPSR0 0xC2
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#define MAC_REG_WAKEUPSR1 0xC3
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#define MAC_REG_WAKE128_0 0xC4
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#define MAC_REG_WAKE128_1 0xD4
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#define MAC_REG_WAKE128_2 0xE4
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#define MAC_REG_WAKE128_3 0xF4
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/************** Page 1 ******************/
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#define MAC_REG_CRC_128_0 0x04
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#define MAC_REG_CRC_128_1 0x06
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#define MAC_REG_CRC_128_2 0x08
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#define MAC_REG_CRC_128_3 0x0A
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/* MAC Configuration Group */
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#define MAC_REG_PAR0 0x0C
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#define MAC_REG_PAR4 0x10
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#define MAC_REG_BSSID0 0x14
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#define MAC_REG_BSSID4 0x18
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#define MAC_REG_MAR0 0x1C
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#define MAC_REG_MAR4 0x20
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/* MAC RSPPKT INFO Group */
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#define MAC_REG_RSPINF_B_1 0x24
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#define MAC_REG_RSPINF_B_2 0x28
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#define MAC_REG_RSPINF_B_5 0x2C
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#define MAC_REG_RSPINF_B_11 0x30
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#define MAC_REG_RSPINF_A_6 0x34
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#define MAC_REG_RSPINF_A_9 0x36
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#define MAC_REG_RSPINF_A_12 0x38
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#define MAC_REG_RSPINF_A_18 0x3A
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#define MAC_REG_RSPINF_A_24 0x3C
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#define MAC_REG_RSPINF_A_36 0x3E
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#define MAC_REG_RSPINF_A_48 0x40
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#define MAC_REG_RSPINF_A_54 0x42
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#define MAC_REG_RSPINF_A_72 0x44
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/* 802.11h relative */
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#define MAC_REG_QUIETINIT 0x60
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#define MAC_REG_QUIETGAP 0x62
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#define MAC_REG_QUIETDUR 0x64
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#define MAC_REG_MSRCTL 0x66
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#define MAC_REG_MSRBBSTS 0x67
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#define MAC_REG_MSRSTART 0x68
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#define MAC_REG_MSRDURATION 0x70
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#define MAC_REG_CCAFRACTION 0x72
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#define MAC_REG_PWRCCK 0x73
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#define MAC_REG_PWROFDM 0x7C
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/* Bits in the BCFG0 register */
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#define BCFG0_PERROFF 0x40
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#define BCFG0_MRDMDIS 0x20
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#define BCFG0_MRDLDIS 0x10
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#define BCFG0_MWMEN 0x08
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#define BCFG0_VSERREN 0x02
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#define BCFG0_LATMEN 0x01
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/* Bits in the BCFG1 register */
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#define BCFG1_CFUNOPT 0x80
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#define BCFG1_CREQOPT 0x40
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#define BCFG1_DMA8 0x10
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#define BCFG1_ARBITOPT 0x08
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#define BCFG1_PCIMEN 0x04
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#define BCFG1_MIOEN 0x02
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#define BCFG1_CISDLYEN 0x01
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/* Bits in RAMBIST registers */
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#define BISTCMD_TSTPAT5 0x00
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#define BISTCMD_TSTPATA 0x80
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#define BISTCMD_TSTERR 0x20
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#define BISTCMD_TSTPATF 0x18
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#define BISTCMD_TSTPAT0 0x10
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#define BISTCMD_TSTMODE 0x04
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#define BISTCMD_TSTITTX 0x03
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#define BISTCMD_TSTATRX 0x02
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#define BISTCMD_TSTATTX 0x01
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#define BISTCMD_TSTRX 0x00
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#define BISTSR0_BISTGO 0x01
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#define BISTSR1_TSTSR 0x01
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#define BISTSR2_CMDPRTEN 0x02
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#define BISTSR2_RAMTSTEN 0x01
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/* Bits in the I2MCFG EEPROM register */
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#define I2MCFG_BOUNDCTL 0x80
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#define I2MCFG_WAITCTL 0x20
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#define I2MCFG_SCLOECTL 0x10
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#define I2MCFG_WBUSYCTL 0x08
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#define I2MCFG_NORETRY 0x04
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#define I2MCFG_I2MLDSEQ 0x02
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#define I2MCFG_I2CMFAST 0x01
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/* Bits in the I2MCSR EEPROM register */
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#define I2MCSR_EEMW 0x80
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#define I2MCSR_EEMR 0x40
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#define I2MCSR_AUTOLD 0x08
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#define I2MCSR_NACK 0x02
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#define I2MCSR_DONE 0x01
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/* Bits in the PMC1 register */
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#define SPS_RST 0x80
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#define PCISTIKY 0x40
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#define PME_OVR 0x02
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/* Bits in the STICKYHW register */
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#define STICKHW_DS1_SHADOW 0x02
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#define STICKHW_DS0_SHADOW 0x01
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/* Bits in the TMCTL register */
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#define TMCTL_TSUSP 0x04
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#define TMCTL_TMD 0x02
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#define TMCTL_TE 0x01
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/* Bits in the TFTCTL register */
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#define TFTCTL_HWUTSF 0x80
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#define TFTCTL_TBTTSYNC 0x40
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#define TFTCTL_HWUTSFEN 0x20
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#define TFTCTL_TSFCNTRRD 0x10
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#define TFTCTL_TBTTSYNCEN 0x08
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#define TFTCTL_TSFSYNCEN 0x04
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#define TFTCTL_TSFCNTRST 0x02
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#define TFTCTL_TSFCNTREN 0x01
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/* Bits in the EnhanceCFG register */
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#define ENCFG_BARKERPREAM 0x00020000
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#define ENCFG_NXTBTTCFPSTR 0x00010000
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#define ENCFG_BCNSUSCLR 0x00000200
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#define ENCFG_BCNSUSIND 0x00000100
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#define ENCFG_CFP_PROTECTEN 0x00000040
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#define ENCFG_PROTECTMD 0x00000020
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#define ENCFG_HWPARCFP 0x00000010
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#define ENCFG_CFNULRSP 0x00000004
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#define ENCFG_BBTYPE_MASK 0x00000003
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#define ENCFG_BBTYPE_G 0x00000002
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#define ENCFG_BBTYPE_B 0x00000001
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#define ENCFG_BBTYPE_A 0x00000000
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/* Bits in the Page1Sel register */
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#define PAGE1_SEL 0x01
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/* Bits in the CFG register */
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#define CFG_TKIPOPT 0x80
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#define CFG_RXDMAOPT 0x40
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#define CFG_TMOT_SW 0x20
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#define CFG_TMOT_HWLONG 0x10
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#define CFG_TMOT_HW 0x00
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#define CFG_CFPENDOPT 0x08
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#define CFG_BCNSUSEN 0x04
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#define CFG_NOTXTIMEOUT 0x02
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#define CFG_NOBUFOPT 0x01
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/* Bits in the TEST register */
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#define TEST_LBEXT 0x80
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#define TEST_LBINT 0x40
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#define TEST_LBNONE 0x00
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#define TEST_SOFTINT 0x20
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#define TEST_CONTTX 0x10
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#define TEST_TXPE 0x08
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#define TEST_NAVDIS 0x04
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#define TEST_NOCTS 0x02
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#define TEST_NOACK 0x01
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/* Bits in the HOSTCR register */
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#define HOSTCR_TXONST 0x80
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#define HOSTCR_RXONST 0x40
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#define HOSTCR_ADHOC 0x20 /* Network Type 1 = Ad-hoc */
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#define HOSTCR_AP 0x10 /* Port Type 1 = AP */
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#define HOSTCR_TXON 0x08 /* 0000 1000 */
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#define HOSTCR_RXON 0x04 /* 0000 0100 */
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#define HOSTCR_MACEN 0x02 /* 0000 0010 */
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#define HOSTCR_SOFTRST 0x01 /* 0000 0001 */
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/* Bits in the MACCR register */
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#define MACCR_SYNCFLUSHOK 0x04
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#define MACCR_SYNCFLUSH 0x02
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#define MACCR_CLRNAV 0x01
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/* Bits in the MAC_REG_GPIOCTL0 register */
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#define LED_ACTSET 0x01
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#define LED_RFOFF 0x02
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#define LED_NOCONNECT 0x04
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/* Bits in the RCR register */
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#define RCR_SSID 0x80
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#define RCR_RXALLTYPE 0x40
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#define RCR_UNICAST 0x20
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#define RCR_BROADCAST 0x10
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#define RCR_MULTICAST 0x08
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#define RCR_WPAERR 0x04
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#define RCR_ERRCRC 0x02
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#define RCR_BSSID 0x01
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/* Bits in the TCR register */
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#define TCR_SYNCDCFOPT 0x02
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#define TCR_AUTOBCNTX 0x01 /* Beacon automatically transmit enable */
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/* Bits in the IMR register */
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#define IMR_MEASURESTART 0x80000000
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#define IMR_QUIETSTART 0x20000000
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#define IMR_RADARDETECT 0x10000000
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#define IMR_MEASUREEND 0x08000000
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#define IMR_SOFTTIMER1 0x00200000
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#define IMR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */
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#define IMR_RXNOBUF 0x00000800
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#define IMR_MIBNEARFULL 0x00000400
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#define IMR_SOFTINT 0x00000200
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#define IMR_FETALERR 0x00000100
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#define IMR_WATCHDOG 0x00000080
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#define IMR_SOFTTIMER 0x00000040
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#define IMR_GPIO 0x00000020
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#define IMR_TBTT 0x00000010
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#define IMR_RXDMA0 0x00000008
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#define IMR_BNTX 0x00000004
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#define IMR_AC0DMA 0x00000002
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#define IMR_TXDMA0 0x00000001
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/* Bits in the ISR register */
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#define ISR_MEASURESTART 0x80000000
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#define ISR_QUIETSTART 0x20000000
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#define ISR_RADARDETECT 0x10000000
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#define ISR_MEASUREEND 0x08000000
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#define ISR_SOFTTIMER1 0x00200000
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#define ISR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */
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#define ISR_RXNOBUF 0x00000800 /* 0000 0000 0000 1000 0000 0000 */
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#define ISR_MIBNEARFULL 0x00000400 /* 0000 0000 0000 0100 0000 0000 */
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#define ISR_SOFTINT 0x00000200
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#define ISR_FETALERR 0x00000100
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#define ISR_WATCHDOG 0x00000080
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#define ISR_SOFTTIMER 0x00000040
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#define ISR_GPIO 0x00000020
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#define ISR_TBTT 0x00000010
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#define ISR_RXDMA0 0x00000008
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#define ISR_BNTX 0x00000004
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#define ISR_AC0DMA 0x00000002
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#define ISR_TXDMA0 0x00000001
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/* Bits in the PSCFG register */
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#define PSCFG_PHILIPMD 0x40
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#define PSCFG_WAKECALEN 0x20
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#define PSCFG_WAKETMREN 0x10
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#define PSCFG_BBPSPROG 0x08
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#define PSCFG_WAKESYN 0x04
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#define PSCFG_SLEEPSYN 0x02
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#define PSCFG_AUTOSLEEP 0x01
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/* Bits in the PSCTL register */
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#define PSCTL_WAKEDONE 0x20
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#define PSCTL_PS 0x10
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#define PSCTL_GO2DOZE 0x08
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#define PSCTL_LNBCN 0x04
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#define PSCTL_ALBCN 0x02
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#define PSCTL_PSEN 0x01
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/* Bits in the PSPWSIG register */
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#define PSSIG_WPE3 0x80
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#define PSSIG_WPE2 0x40
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#define PSSIG_WPE1 0x20
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#define PSSIG_WRADIOPE 0x10
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#define PSSIG_SPE3 0x08
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#define PSSIG_SPE2 0x04
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#define PSSIG_SPE1 0x02
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#define PSSIG_SRADIOPE 0x01
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/* Bits in the BBREGCTL register */
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#define BBREGCTL_DONE 0x04
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#define BBREGCTL_REGR 0x02
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#define BBREGCTL_REGW 0x01
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/* Bits in the IFREGCTL register */
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#define IFREGCTL_DONE 0x04
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#define IFREGCTL_IFRF 0x02
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#define IFREGCTL_REGW 0x01
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/* Bits in the SOFTPWRCTL register */
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#define SOFTPWRCTL_RFLEOPT 0x0800
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#define SOFTPWRCTL_TXPEINV 0x0200
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#define SOFTPWRCTL_SWPECTI 0x0100
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#define SOFTPWRCTL_SWPAPE 0x0020
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#define SOFTPWRCTL_SWCALEN 0x0010
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#define SOFTPWRCTL_SWRADIO_PE 0x0008
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#define SOFTPWRCTL_SWPE2 0x0004
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#define SOFTPWRCTL_SWPE1 0x0002
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#define SOFTPWRCTL_SWPE3 0x0001
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/* Bits in the GPIOCTL1 register */
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#define GPIO1_DATA1 0x20
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#define GPIO1_MD1 0x10
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#define GPIO1_DATA0 0x02
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#define GPIO1_MD0 0x01
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/* Bits in the DMACTL register */
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#define DMACTL_CLRRUN 0x00080000
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#define DMACTL_RUN 0x00000008
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#define DMACTL_WAKE 0x00000004
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#define DMACTL_DEAD 0x00000002
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#define DMACTL_ACTIVE 0x00000001
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/* Bits in the RXDMACTL0 register */
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#define RX_PERPKT 0x00000100
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#define RX_PERPKTCLR 0x01000000
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/* Bits in the BCNDMACTL register */
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#define BEACON_READY 0x01
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/* Bits in the MISCFFCTL register */
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#define MISCFFCTL_WRITE 0x0001
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/* Bits in WAKEUPEN0 */
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#define WAKEUPEN0_DIRPKT 0x10
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#define WAKEUPEN0_LINKOFF 0x08
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#define WAKEUPEN0_ATIMEN 0x04
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#define WAKEUPEN0_TIMEN 0x02
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#define WAKEUPEN0_MAGICEN 0x01
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/* Bits in WAKEUPEN1 */
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#define WAKEUPEN1_128_3 0x08
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#define WAKEUPEN1_128_2 0x04
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#define WAKEUPEN1_128_1 0x02
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#define WAKEUPEN1_128_0 0x01
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/* Bits in WAKEUPSR0 */
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#define WAKEUPSR0_DIRPKT 0x10
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#define WAKEUPSR0_LINKOFF 0x08
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#define WAKEUPSR0_ATIMEN 0x04
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#define WAKEUPSR0_TIMEN 0x02
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#define WAKEUPSR0_MAGICEN 0x01
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/* Bits in WAKEUPSR1 */
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#define WAKEUPSR1_128_3 0x08
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#define WAKEUPSR1_128_2 0x04
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#define WAKEUPSR1_128_1 0x02
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#define WAKEUPSR1_128_0 0x01
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/* Bits in the MAC_REG_GPIOCTL register */
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#define GPIO0_MD 0x01
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#define GPIO0_DATA 0x02
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#define GPIO0_INTMD 0x04
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#define GPIO1_MD 0x10
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#define GPIO1_DATA 0x20
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/* Bits in the MSRCTL register */
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#define MSRCTL_FINISH 0x80
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#define MSRCTL_READY 0x40
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#define MSRCTL_RADARDETECT 0x20
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#define MSRCTL_EN 0x10
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#define MSRCTL_QUIETTXCHK 0x08
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#define MSRCTL_QUIETRPT 0x04
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#define MSRCTL_QUIETINT 0x02
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#define MSRCTL_QUIETEN 0x01
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/* Bits in the MSRCTL1 register */
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#define MSRCTL1_TXPWR 0x08
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#define MSRCTL1_CSAPAREN 0x04
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#define MSRCTL1_TXPAUSE 0x01
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/* Loopback mode */
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#define MAC_LB_EXT 0x02
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#define MAC_LB_INTERNAL 0x01
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#define MAC_LB_NONE 0x00
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#define DEFAULT_BI 0x200
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/* MiscFIFO Offset */
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#define MISCFIFO_KEYETRY0 32
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#define MISCFIFO_KEYENTRYSIZE 22
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#define MISCFIFO_SYNINFO_IDX 10
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#define MISCFIFO_SYNDATA_IDX 11
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#define MISCFIFO_SYNDATASIZE 21
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/* enabled mask value of irq */
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#define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
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IMR_RXDMA1 | \
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IMR_RXNOBUF | \
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IMR_MIBNEARFULL | \
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IMR_SOFTINT | \
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IMR_FETALERR | \
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IMR_WATCHDOG | \
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IMR_SOFTTIMER | \
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IMR_GPIO | \
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IMR_TBTT | \
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IMR_RXDMA0 | \
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IMR_BNTX | \
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IMR_AC0DMA | \
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IMR_TXDMA0)
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/* max time out delay time */
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#define W_MAX_TIMEOUT 0xFFF0U
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/* wait time within loop */
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#define CB_DELAY_LOOP_WAIT 10 /* 10ms */
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/* revision id */
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#define REV_ID_VT3253_A0 0x00
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#define REV_ID_VT3253_A1 0x01
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#define REV_ID_VT3253_B0 0x08
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#define REV_ID_VT3253_B1 0x09
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/*--------------------- Export Types ------------------------------*/
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/*--------------------- Export Macros ------------------------------*/
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#define MACvReceive0(iobase) \
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do { \
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unsigned long dwData; \
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dwData = ioread32(iobase + MAC_REG_RXDMACTL0); \
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if (dwData & DMACTL_RUN) \
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iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL0); \
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else \
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iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL0); \
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} while (0)
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#define MACvReceive1(iobase) \
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do { \
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unsigned long dwData; \
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dwData = ioread32(iobase + MAC_REG_RXDMACTL1); \
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if (dwData & DMACTL_RUN) \
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iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL1); \
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else \
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iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL1); \
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} while (0)
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#define MACvTransmit0(iobase) \
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do { \
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unsigned long dwData; \
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dwData = ioread32(iobase + MAC_REG_TXDMACTL0); \
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if (dwData & DMACTL_RUN) \
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iowrite32(DMACTL_WAKE, iobase + MAC_REG_TXDMACTL0); \
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else \
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iowrite32(DMACTL_RUN, iobase + MAC_REG_TXDMACTL0); \
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} while (0)
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#define MACvTransmitAC0(iobase) \
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do { \
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unsigned long dwData; \
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dwData = ioread32(iobase + MAC_REG_AC0DMACTL); \
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if (dwData & DMACTL_RUN) \
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iowrite32(DMACTL_WAKE, iobase + MAC_REG_AC0DMACTL); \
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else \
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iowrite32(DMACTL_RUN, iobase + MAC_REG_AC0DMACTL); \
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} while (0)
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#define MACvSelectPage0(iobase) \
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iowrite8(0, iobase + MAC_REG_PAGE1SEL)
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#define MACvSelectPage1(iobase) \
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iowrite8(1, iobase + MAC_REG_PAGE1SEL)
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#define MACvEnableProtectMD(iobase) \
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do { \
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unsigned long dwOrgValue; \
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dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
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dwOrgValue = dwOrgValue | ENCFG_PROTECTMD; \
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iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
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} while (0)
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#define MACvDisableProtectMD(iobase) \
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do { \
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unsigned long dwOrgValue; \
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dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
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dwOrgValue = dwOrgValue & ~ENCFG_PROTECTMD; \
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iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
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} while (0)
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#define MACvEnableBarkerPreambleMd(iobase) \
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do { \
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unsigned long dwOrgValue; \
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dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
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dwOrgValue = dwOrgValue | ENCFG_BARKERPREAM; \
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iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
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} while (0)
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#define MACvDisableBarkerPreambleMd(iobase) \
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do { \
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unsigned long dwOrgValue; \
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dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
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dwOrgValue = dwOrgValue & ~ENCFG_BARKERPREAM; \
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iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
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} while (0)
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#define MACvSetBBType(iobase, byTyp) \
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do { \
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unsigned long dwOrgValue; \
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dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
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|
dwOrgValue = dwOrgValue & ~ENCFG_BBTYPE_MASK; \
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dwOrgValue = dwOrgValue | (unsigned long)byTyp; \
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iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
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} while (0)
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#define MACvSetRFLE_LatchBase(iobase) \
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vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
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|
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#define MAKEWORD(lb, hb) \
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((unsigned short)(((unsigned char)(lb)) | (((unsigned short)((unsigned char)(hb))) << 8)))
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void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask);
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void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask);
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void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask);
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void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask);
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|
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bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
|
|
unsigned char byTestBits);
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|
bool MACbIsIntDisable(struct vnt_private *priv);
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|
|
void MACvSetShortRetryLimit(struct vnt_private *priv,
|
|
unsigned char byRetryLimit);
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void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit);
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void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode);
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void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf);
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void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf);
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|
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bool MACbSoftwareReset(struct vnt_private *priv);
|
|
bool MACbSafeSoftwareReset(struct vnt_private *priv);
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|
bool MACbSafeRxOff(struct vnt_private *priv);
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|
bool MACbSafeTxOff(struct vnt_private *priv);
|
|
bool MACbSafeStop(struct vnt_private *priv);
|
|
bool MACbShutdown(struct vnt_private *priv);
|
|
void MACvInitialize(struct vnt_private *priv);
|
|
void MACvSetCurrRx0DescAddr(struct vnt_private *priv,
|
|
u32 curr_desc_addr);
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|
void MACvSetCurrRx1DescAddr(struct vnt_private *priv,
|
|
u32 curr_desc_addr);
|
|
void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
|
|
u32 curr_desc_addr);
|
|
void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
|
|
u32 curr_desc_addr);
|
|
void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
|
|
u32 curr_desc_addr);
|
|
void MACvSetCurrSyncDescAddrEx(struct vnt_private *priv,
|
|
u32 curr_desc_addr);
|
|
void MACvSetCurrATIMDescAddrEx(struct vnt_private *priv,
|
|
u32 curr_desc_addr);
|
|
void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay);
|
|
void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime);
|
|
|
|
void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset,
|
|
u32 dwData);
|
|
|
|
bool MACbPSWakeup(struct vnt_private *priv);
|
|
|
|
void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
|
|
unsigned int uEntryIdx, unsigned int uKeyIdx,
|
|
unsigned char *pbyAddr, u32 *pdwKey,
|
|
unsigned char local_id);
|
|
void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx);
|
|
|
|
#endif /* __MAC_H__ */
|