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![Hongtao Jia](/assets/img/avatar_default.png)
Register the qoriq cpufreq driver as a cooling device, based on the thermal device tree framework. When temperature crosses the passive trip point cpufreq is used to throttle CPUs. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
408 lines
9 KiB
C
408 lines
9 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* CPU Frequency Scaling driver for Freescale QorIQ SoCs.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/cpu_cooling.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#if !defined(CONFIG_ARM)
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#include <asm/smp.h> /* for get_hard_smp_processor_id() in UP configs */
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#endif
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/**
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* struct cpu_data
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* @pclk: the parent clock of cpu
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* @table: frequency table
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*/
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struct cpu_data {
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struct clk **pclk;
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struct cpufreq_frequency_table *table;
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struct thermal_cooling_device *cdev;
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};
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/**
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* struct soc_data - SoC specific data
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* @freq_mask: mask the disallowed frequencies
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* @flag: unique flags
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*/
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struct soc_data {
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u32 freq_mask[4];
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u32 flag;
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};
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#define FREQ_MASK 1
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/* see hardware specification for the allowed frqeuencies */
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static const struct soc_data sdata[] = {
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{ /* used by p2041 and p3041 */
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.freq_mask = {0x8, 0x8, 0x2, 0x2},
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.flag = FREQ_MASK,
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},
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{ /* used by p5020 */
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.freq_mask = {0x8, 0x2},
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.flag = FREQ_MASK,
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},
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{ /* used by p4080, p5040 */
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.freq_mask = {0},
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.flag = 0,
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},
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};
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/*
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* the minimum allowed core frequency, in Hz
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* for chassis v1.0, >= platform frequency
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* for chassis v2.0, >= platform frequency / 2
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*/
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static u32 min_cpufreq;
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static const u32 *fmask;
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#if defined(CONFIG_ARM)
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static int get_cpu_physical_id(int cpu)
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{
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return topology_core_id(cpu);
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}
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#else
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static int get_cpu_physical_id(int cpu)
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{
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return get_hard_smp_processor_id(cpu);
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}
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#endif
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static u32 get_bus_freq(void)
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{
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struct device_node *soc;
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u32 sysfreq;
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soc = of_find_node_by_type(NULL, "soc");
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if (!soc)
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return 0;
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if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
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sysfreq = 0;
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of_node_put(soc);
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return sysfreq;
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}
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static struct device_node *cpu_to_clk_node(int cpu)
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{
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struct device_node *np, *clk_np;
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if (!cpu_present(cpu))
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return NULL;
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np = of_get_cpu_node(cpu, NULL);
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if (!np)
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return NULL;
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clk_np = of_parse_phandle(np, "clocks", 0);
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if (!clk_np)
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return NULL;
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of_node_put(np);
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return clk_np;
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}
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/* traverse cpu nodes to get cpu mask of sharing clock wire */
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static void set_affected_cpus(struct cpufreq_policy *policy)
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{
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struct device_node *np, *clk_np;
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struct cpumask *dstp = policy->cpus;
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int i;
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np = cpu_to_clk_node(policy->cpu);
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if (!np)
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return;
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for_each_present_cpu(i) {
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clk_np = cpu_to_clk_node(i);
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if (!clk_np)
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continue;
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if (clk_np == np)
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cpumask_set_cpu(i, dstp);
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of_node_put(clk_np);
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}
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of_node_put(np);
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}
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/* reduce the duplicated frequencies in frequency table */
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static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
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int count)
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{
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int i, j;
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for (i = 1; i < count; i++) {
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for (j = 0; j < i; j++) {
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if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID ||
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freq_table[j].frequency !=
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freq_table[i].frequency)
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continue;
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freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
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break;
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}
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}
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}
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/* sort the frequencies in frequency table in descenting order */
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static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
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int count)
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{
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int i, j, ind;
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unsigned int freq, max_freq;
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struct cpufreq_frequency_table table;
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for (i = 0; i < count - 1; i++) {
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max_freq = freq_table[i].frequency;
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ind = i;
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for (j = i + 1; j < count; j++) {
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freq = freq_table[j].frequency;
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if (freq == CPUFREQ_ENTRY_INVALID ||
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freq <= max_freq)
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continue;
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ind = j;
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max_freq = freq;
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}
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if (ind != i) {
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/* exchange the frequencies */
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table.driver_data = freq_table[i].driver_data;
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table.frequency = freq_table[i].frequency;
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freq_table[i].driver_data = freq_table[ind].driver_data;
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freq_table[i].frequency = freq_table[ind].frequency;
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freq_table[ind].driver_data = table.driver_data;
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freq_table[ind].frequency = table.frequency;
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}
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}
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}
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static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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struct device_node *np, *pnode;
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int i, count, ret;
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u32 freq, mask;
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struct clk *clk;
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struct cpufreq_frequency_table *table;
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struct cpu_data *data;
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unsigned int cpu = policy->cpu;
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u64 u64temp;
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np = of_get_cpu_node(cpu, NULL);
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if (!np)
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return -ENODEV;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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goto err_np;
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policy->clk = of_clk_get(np, 0);
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if (IS_ERR(policy->clk)) {
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pr_err("%s: no clock information\n", __func__);
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goto err_nomem2;
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}
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pnode = of_parse_phandle(np, "clocks", 0);
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if (!pnode) {
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pr_err("%s: could not get clock information\n", __func__);
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goto err_nomem2;
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}
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count = of_property_count_strings(pnode, "clock-names");
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data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
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if (!data->pclk) {
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pr_err("%s: no memory\n", __func__);
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goto err_node;
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}
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table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
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if (!table) {
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pr_err("%s: no memory\n", __func__);
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goto err_pclk;
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}
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if (fmask)
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mask = fmask[get_cpu_physical_id(cpu)];
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else
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mask = 0x0;
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for (i = 0; i < count; i++) {
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clk = of_clk_get(pnode, i);
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data->pclk[i] = clk;
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freq = clk_get_rate(clk);
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/*
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* the clock is valid if its frequency is not masked
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* and large than minimum allowed frequency.
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*/
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if (freq < min_cpufreq || (mask & (1 << i)))
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table[i].frequency = CPUFREQ_ENTRY_INVALID;
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else
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table[i].frequency = freq / 1000;
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table[i].driver_data = i;
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}
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freq_table_redup(table, count);
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freq_table_sort(table, count);
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table[i].frequency = CPUFREQ_TABLE_END;
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/* set the min and max frequency properly */
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ret = cpufreq_table_validate_and_show(policy, table);
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if (ret) {
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pr_err("invalid frequency table: %d\n", ret);
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goto err_nomem1;
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}
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data->table = table;
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/* update ->cpus if we have cluster, no harm if not */
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set_affected_cpus(policy);
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policy->driver_data = data;
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/* Minimum transition latency is 12 platform clocks */
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u64temp = 12ULL * NSEC_PER_SEC;
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do_div(u64temp, get_bus_freq());
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policy->cpuinfo.transition_latency = u64temp + 1;
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of_node_put(np);
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of_node_put(pnode);
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return 0;
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err_nomem1:
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kfree(table);
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err_pclk:
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kfree(data->pclk);
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err_node:
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of_node_put(pnode);
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err_nomem2:
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policy->driver_data = NULL;
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kfree(data);
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err_np:
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of_node_put(np);
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return -ENODEV;
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}
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static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
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{
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struct cpu_data *data = policy->driver_data;
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kfree(data->pclk);
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kfree(data->table);
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kfree(data);
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policy->driver_data = NULL;
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return 0;
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}
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static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct clk *parent;
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struct cpu_data *data = policy->driver_data;
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parent = data->pclk[data->table[index].driver_data];
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return clk_set_parent(policy->clk, parent);
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}
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static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
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{
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struct cpu_data *cpud = policy->driver_data;
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struct device_node *np = of_get_cpu_node(policy->cpu, NULL);
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if (of_find_property(np, "#cooling-cells", NULL)) {
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cpud->cdev = of_cpufreq_cooling_register(np,
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policy->related_cpus);
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if (IS_ERR(cpud->cdev)) {
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pr_err("Failed to register cooling device cpu%d: %ld\n",
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policy->cpu, PTR_ERR(cpud->cdev));
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cpud->cdev = NULL;
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}
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}
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of_node_put(np);
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}
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static struct cpufreq_driver qoriq_cpufreq_driver = {
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.name = "qoriq_cpufreq",
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.flags = CPUFREQ_CONST_LOOPS,
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.init = qoriq_cpufreq_cpu_init,
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.exit = __exit_p(qoriq_cpufreq_cpu_exit),
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = qoriq_cpufreq_target,
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.get = cpufreq_generic_get,
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.ready = qoriq_cpufreq_ready,
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.attr = cpufreq_generic_attr,
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};
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static const struct of_device_id node_matches[] __initconst = {
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{ .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
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{ .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
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{ .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
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{ .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
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{ .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
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{ .compatible = "fsl,qoriq-clockgen-2.0", },
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{}
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};
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static int __init qoriq_cpufreq_init(void)
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{
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int ret;
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struct device_node *np;
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const struct of_device_id *match;
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const struct soc_data *data;
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np = of_find_matching_node(NULL, node_matches);
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if (!np)
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return -ENODEV;
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match = of_match_node(node_matches, np);
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data = match->data;
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if (data) {
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if (data->flag)
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fmask = data->freq_mask;
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min_cpufreq = get_bus_freq();
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} else {
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min_cpufreq = get_bus_freq() / 2;
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}
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of_node_put(np);
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ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
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if (!ret)
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pr_info("Freescale QorIQ CPU frequency scaling driver\n");
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return ret;
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}
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module_init(qoriq_cpufreq_init);
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static void __exit qoriq_cpufreq_exit(void)
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{
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cpufreq_unregister_driver(&qoriq_cpufreq_driver);
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}
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module_exit(qoriq_cpufreq_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
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MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
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