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![Christoph Hellwig](/assets/img/avatar_default.png)
Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Nicholas Bellinger <nab@linux-iscsi.org>
797 lines
20 KiB
C
797 lines
20 KiB
C
/*
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* drivers/misc/spear13xx_pcie_gadget.c
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*
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* Copyright (C) 2010 ST Microelectronics
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* Pratyush Anand<pratyush.anand@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pci_regs.h>
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#include <linux/configfs.h>
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#include <mach/pcie.h>
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#include <mach/misc_regs.h>
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#define IN0_MEM_SIZE (200 * 1024 * 1024 - 1)
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/* In current implementation address translation is done using IN0 only.
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* So IN1 start address and IN0 end address has been kept same
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*/
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#define IN1_MEM_SIZE (0 * 1024 * 1024 - 1)
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#define IN_IO_SIZE (20 * 1024 * 1024 - 1)
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#define IN_CFG0_SIZE (12 * 1024 * 1024 - 1)
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#define IN_CFG1_SIZE (12 * 1024 * 1024 - 1)
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#define IN_MSG_SIZE (12 * 1024 * 1024 - 1)
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/* Keep default BAR size as 4K*/
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/* AORAM would be mapped by default*/
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#define INBOUND_ADDR_MASK (SPEAR13XX_SYSRAM1_SIZE - 1)
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#define INT_TYPE_NO_INT 0
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#define INT_TYPE_INTX 1
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#define INT_TYPE_MSI 2
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struct spear_pcie_gadget_config {
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void __iomem *base;
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void __iomem *va_app_base;
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void __iomem *va_dbi_base;
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char int_type[10];
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ulong requested_msi;
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ulong configured_msi;
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ulong bar0_size;
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ulong bar0_rw_offset;
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void __iomem *va_bar0_address;
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};
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struct pcie_gadget_target {
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struct configfs_subsystem subsys;
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struct spear_pcie_gadget_config config;
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};
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struct pcie_gadget_target_attr {
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struct configfs_attribute attr;
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ssize_t (*show)(struct spear_pcie_gadget_config *config,
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char *buf);
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ssize_t (*store)(struct spear_pcie_gadget_config *config,
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const char *buf,
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size_t count);
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};
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static void enable_dbi_access(struct pcie_app_reg __iomem *app_reg)
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{
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/* Enable DBI access */
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writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID),
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&app_reg->slv_armisc);
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writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID),
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&app_reg->slv_awmisc);
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}
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static void disable_dbi_access(struct pcie_app_reg __iomem *app_reg)
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{
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/* disable DBI access */
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writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),
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&app_reg->slv_armisc);
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writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),
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&app_reg->slv_awmisc);
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}
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static void spear_dbi_read_reg(struct spear_pcie_gadget_config *config,
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int where, int size, u32 *val)
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{
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struct pcie_app_reg __iomem *app_reg = config->va_app_base;
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ulong va_address;
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/* Enable DBI access */
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enable_dbi_access(app_reg);
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va_address = (ulong)config->va_dbi_base + (where & ~0x3);
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*val = readl(va_address);
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 3))) & 0xffff;
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/* Disable DBI access */
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disable_dbi_access(app_reg);
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}
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static void spear_dbi_write_reg(struct spear_pcie_gadget_config *config,
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int where, int size, u32 val)
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{
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struct pcie_app_reg __iomem *app_reg = config->va_app_base;
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ulong va_address;
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/* Enable DBI access */
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enable_dbi_access(app_reg);
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va_address = (ulong)config->va_dbi_base + (where & ~0x3);
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if (size == 4)
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writel(val, va_address);
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else if (size == 2)
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writew(val, va_address + (where & 2));
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else if (size == 1)
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writeb(val, va_address + (where & 3));
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/* Disable DBI access */
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disable_dbi_access(app_reg);
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}
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#define PCI_FIND_CAP_TTL 48
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static int pci_find_own_next_cap_ttl(struct spear_pcie_gadget_config *config,
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u32 pos, int cap, int *ttl)
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{
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u32 id;
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while ((*ttl)--) {
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spear_dbi_read_reg(config, pos, 1, &pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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spear_dbi_read_reg(config, pos + PCI_CAP_LIST_ID, 1, &id);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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static int pci_find_own_next_cap(struct spear_pcie_gadget_config *config,
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u32 pos, int cap)
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{
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int ttl = PCI_FIND_CAP_TTL;
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return pci_find_own_next_cap_ttl(config, pos, cap, &ttl);
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}
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static int pci_find_own_cap_start(struct spear_pcie_gadget_config *config,
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u8 hdr_type)
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{
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u32 status;
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spear_dbi_read_reg(config, PCI_STATUS, 2, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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switch (hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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return PCI_CAPABILITY_LIST;
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case PCI_HEADER_TYPE_CARDBUS:
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return PCI_CB_CAPABILITY_LIST;
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default:
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return 0;
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}
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return 0;
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}
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/*
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* Tell if a device supports a given PCI capability.
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it. Possible values for @cap:
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*
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* %PCI_CAP_ID_PM Power Management
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* %PCI_CAP_ID_AGP Accelerated Graphics Port
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* %PCI_CAP_ID_VPD Vital Product Data
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* %PCI_CAP_ID_SLOTID Slot Identification
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* %PCI_CAP_ID_MSI Message Signalled Interrupts
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* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
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* %PCI_CAP_ID_PCIX PCI-X
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* %PCI_CAP_ID_EXP PCI Express
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*/
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static int pci_find_own_capability(struct spear_pcie_gadget_config *config,
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int cap)
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{
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u32 pos;
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u32 hdr_type;
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spear_dbi_read_reg(config, PCI_HEADER_TYPE, 1, &hdr_type);
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pos = pci_find_own_cap_start(config, hdr_type);
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if (pos)
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pos = pci_find_own_next_cap(config, pos, cap);
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return pos;
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}
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static irqreturn_t spear_pcie_gadget_irq(int irq, void *dev_id)
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{
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return 0;
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}
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/*
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* configfs interfaces show/store functions
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*/
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static struct pcie_gadget_target *to_target(struct config_item *item)
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{
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return item ?
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container_of(to_configfs_subsystem(to_config_group(item)),
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struct pcie_gadget_target, subsys) : NULL;
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}
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static ssize_t pcie_gadget_link_show(struct config_item *item, char *buf)
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{
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struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;
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if (readl(&app_reg->app_status_1) & ((u32)1 << XMLH_LINK_UP_ID))
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return sprintf(buf, "UP");
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else
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return sprintf(buf, "DOWN");
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}
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static ssize_t pcie_gadget_link_store(struct config_item *item,
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const char *buf, size_t count)
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{
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struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;
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if (sysfs_streq(buf, "UP"))
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writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID),
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&app_reg->app_ctrl_0);
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else if (sysfs_streq(buf, "DOWN"))
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writel(readl(&app_reg->app_ctrl_0)
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& ~(1 << APP_LTSSM_ENABLE_ID),
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&app_reg->app_ctrl_0);
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else
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return -EINVAL;
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return count;
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}
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static ssize_t pcie_gadget_int_type_show(struct config_item *item, char *buf)
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{
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return sprintf(buf, "%s", to_target(item)->int_type);
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}
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static ssize_t pcie_gadget_int_type_store(struct config_item *item,
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const char *buf, size_t count)
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{
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struct spear_pcie_gadget_config *config = to_target(item)
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u32 cap, vec, flags;
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ulong vector;
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if (sysfs_streq(buf, "INTA"))
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spear_dbi_write_reg(config, PCI_INTERRUPT_LINE, 1, 1);
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else if (sysfs_streq(buf, "MSI")) {
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vector = config->requested_msi;
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vec = 0;
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while (vector > 1) {
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vector /= 2;
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vec++;
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}
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spear_dbi_write_reg(config, PCI_INTERRUPT_LINE, 1, 0);
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cap = pci_find_own_capability(config, PCI_CAP_ID_MSI);
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spear_dbi_read_reg(config, cap + PCI_MSI_FLAGS, 1, &flags);
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flags &= ~PCI_MSI_FLAGS_QMASK;
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flags |= vec << 1;
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spear_dbi_write_reg(config, cap + PCI_MSI_FLAGS, 1, flags);
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} else
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return -EINVAL;
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strcpy(config->int_type, buf);
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return count;
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}
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static ssize_t pcie_gadget_no_of_msi_show(struct config_item *item, char *buf)
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{
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struct spear_pcie_gadget_config *config = to_target(item)
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struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;
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u32 cap, vec, flags;
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ulong vector;
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if ((readl(&app_reg->msg_status) & (1 << CFG_MSI_EN_ID))
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!= (1 << CFG_MSI_EN_ID))
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vector = 0;
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else {
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cap = pci_find_own_capability(config, PCI_CAP_ID_MSI);
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spear_dbi_read_reg(config, cap + PCI_MSI_FLAGS, 1, &flags);
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flags &= ~PCI_MSI_FLAGS_QSIZE;
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vec = flags >> 4;
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vector = 1;
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while (vec--)
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vector *= 2;
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}
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config->configured_msi = vector;
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return sprintf(buf, "%lu", vector);
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}
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static ssize_t pcie_gadget_no_of_msi_store(struct config_item *item,
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const char *buf, size_t count)
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{
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int ret;
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ret = kstrtoul(buf, 0, &to_target(item)->requested_msi);
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if (ret)
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return ret;
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if (config->requested_msi > 32)
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config->requested_msi = 32;
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return count;
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}
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static ssize_t pcie_gadget_inta_store(struct config_item *item,
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const char *buf, size_t count)
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{
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struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;
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ulong en;
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int ret;
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ret = kstrtoul(buf, 0, &en);
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if (ret)
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return ret;
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if (en)
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writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID),
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&app_reg->app_ctrl_0);
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else
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writel(readl(&app_reg->app_ctrl_0) & ~(1 << SYS_INT_ID),
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&app_reg->app_ctrl_0);
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return count;
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}
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static ssize_t pcie_gadget_send_msi_store(struct config_item *item,
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const char *buf, size_t count)
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{
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struct spear_pcie_gadget_config *config = to_target(item)
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struct pcie_app_reg __iomem *app_reg = config->va_app_base;
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ulong vector;
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u32 ven_msi;
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int ret;
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ret = kstrtoul(buf, 0, &vector);
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if (ret)
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return ret;
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if (!config->configured_msi)
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return -EINVAL;
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if (vector >= config->configured_msi)
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return -EINVAL;
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ven_msi = readl(&app_reg->ven_msi_1);
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ven_msi &= ~VEN_MSI_FUN_NUM_MASK;
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ven_msi |= 0 << VEN_MSI_FUN_NUM_ID;
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ven_msi &= ~VEN_MSI_TC_MASK;
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ven_msi |= 0 << VEN_MSI_TC_ID;
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ven_msi &= ~VEN_MSI_VECTOR_MASK;
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ven_msi |= vector << VEN_MSI_VECTOR_ID;
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/* generating interrupt for msi vector */
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ven_msi |= VEN_MSI_REQ_EN;
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writel(ven_msi, &app_reg->ven_msi_1);
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udelay(1);
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ven_msi &= ~VEN_MSI_REQ_EN;
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writel(ven_msi, &app_reg->ven_msi_1);
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return count;
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}
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static ssize_t pcie_gadget_vendor_id_show(struct config_item *item, char *buf)
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{
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u32 id;
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spear_dbi_read_reg(to_target(item), PCI_VENDOR_ID, 2, &id);
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return sprintf(buf, "%x", id);
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}
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static ssize_t pcie_gadget_vendor_id_store(struct config_item *item,
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const char *buf, size_t count)
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{
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ulong id;
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int ret;
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ret = kstrtoul(buf, 0, &id);
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if (ret)
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return ret;
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spear_dbi_write_reg(to_target(item), PCI_VENDOR_ID, 2, id);
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return count;
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}
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static ssize_t pcie_gadget_device_id_show(struct config_item *item, char *buf)
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{
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u32 id;
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spear_dbi_read_reg(to_target(item), PCI_DEVICE_ID, 2, &id);
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return sprintf(buf, "%x", id);
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}
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static ssize_t pcie_gadget_device_id_store(struct config_item *item,
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const char *buf, size_t count)
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{
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ulong id;
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int ret;
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ret = kstrtoul(buf, 0, &id);
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if (ret)
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return ret;
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spear_dbi_write_reg(to_target(item), PCI_DEVICE_ID, 2, id);
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return count;
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}
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static ssize_t pcie_gadget_bar0_size_show(struct config_item *item, char *buf)
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{
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return sprintf(buf, "%lx", to_target(item)->bar0_size);
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}
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static ssize_t pcie_gadget_bar0_size_store(struct config_item *item,
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const char *buf, size_t count)
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{
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struct spear_pcie_gadget_config *config = to_target(item)
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ulong size;
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u32 pos, pos1;
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u32 no_of_bit = 0;
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int ret;
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ret = kstrtoul(buf, 0, &size);
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if (ret)
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return ret;
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/* min bar size is 256 */
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if (size <= 0x100)
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size = 0x100;
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/* max bar size is 1MB*/
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else if (size >= 0x100000)
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size = 0x100000;
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else {
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pos = 0;
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pos1 = 0;
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while (pos < 21) {
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pos = find_next_bit((ulong *)&size, 21, pos);
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if (pos != 21)
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pos1 = pos + 1;
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pos++;
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no_of_bit++;
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}
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if (no_of_bit == 2)
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pos1--;
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size = 1 << pos1;
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}
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config->bar0_size = size;
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spear_dbi_write_reg(config, PCIE_BAR0_MASK_REG, 4, size - 1);
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return count;
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}
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static ssize_t pcie_gadget_bar0_address_show(struct config_item *item,
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char *buf)
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{
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struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;
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u32 address = readl(&app_reg->pim0_mem_addr_start);
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return sprintf(buf, "%x", address);
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}
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static ssize_t pcie_gadget_bar0_address_store(struct config_item *item,
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const char *buf, size_t count)
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{
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struct spear_pcie_gadget_config *config = to_target(item)
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struct pcie_app_reg __iomem *app_reg = config->va_app_base;
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ulong address;
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int ret;
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ret = kstrtoul(buf, 0, &address);
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if (ret)
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return ret;
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address &= ~(config->bar0_size - 1);
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if (config->va_bar0_address)
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iounmap(config->va_bar0_address);
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config->va_bar0_address = ioremap(address, config->bar0_size);
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if (!config->va_bar0_address)
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return -ENOMEM;
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writel(address, &app_reg->pim0_mem_addr_start);
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return count;
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}
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static ssize_t pcie_gadget_bar0_rw_offset_show(struct config_item *item,
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char *buf)
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{
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return sprintf(buf, "%lx", to_target(item)->bar0_rw_offset);
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}
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static ssize_t pcie_gadget_bar0_rw_offset_store(struct config_item *item,
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const char *buf, size_t count)
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{
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ulong offset;
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int ret;
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ret = kstrtoul(buf, 0, &offset);
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if (ret)
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return ret;
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if (offset % 4)
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return -EINVAL;
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to_target(item)->bar0_rw_offset = offset;
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return count;
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}
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static ssize_t pcie_gadget_bar0_data_show(struct config_item *item, char *buf)
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{
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struct spear_pcie_gadget_config *config = to_target(item)
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ulong data;
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if (!config->va_bar0_address)
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return -ENOMEM;
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data = readl((ulong)config->va_bar0_address + config->bar0_rw_offset);
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return sprintf(buf, "%lx", data);
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}
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static ssize_t pcie_gadget_bar0_data_store(struct config_item *item,
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const char *buf, size_t count)
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{
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struct spear_pcie_gadget_config *config = to_target(item)
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ulong data;
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int ret;
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ret = kstrtoul(buf, 0, &data);
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if (ret)
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return ret;
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if (!config->va_bar0_address)
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return -ENOMEM;
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writel(data, (ulong)config->va_bar0_address + config->bar0_rw_offset);
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return count;
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}
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CONFIGFS_ATTR(pcie_gadget_, link);
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CONFIGFS_ATTR(pcie_gadget_, int_type);
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CONFIGFS_ATTR(pcie_gadget_, no_of_msi);
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CONFIGFS_ATTR_WO(pcie_gadget_, inta);
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CONFIGFS_ATTR_WO(pcie_gadget_, send_msi);
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CONFIGFS_ATTR(pcie_gadget_, vendor_id);
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CONFIGFS_ATTR(pcie_gadget_, device_id);
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CONFIGFS_ATTR(pcie_gadget_, bar0_size);
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CONFIGFS_ATTR(pcie_gadget_, bar0_address);
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CONFIGFS_ATTR(pcie_gadget_, bar0_rw_offset);
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CONFIGFS_ATTR(pcie_gadget_, bar0_data);
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static struct configfs_attribute *pcie_gadget_target_attrs[] = {
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&pcie_gadget_attr_link,
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&pcie_gadget_attr_int_type,
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&pcie_gadget_attr_no_of_msi,
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&pcie_gadget_attr_inta,
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&pcie_gadget_attr_send_msi,
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&pcie_gadget_attr_vendor_id,
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&pcie_gadget_attr_device_id,
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&pcie_gadget_attr_bar0_size,
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&pcie_gadget_attr_bar0_address,
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&pcie_gadget_attr_bar0_rw_offset,
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&pcie_gadget_attr_bar0_data,
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NULL,
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};
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static struct config_item_type pcie_gadget_target_type = {
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.ct_attrs = pcie_gadget_target_attrs,
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.ct_owner = THIS_MODULE,
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};
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static void spear13xx_pcie_device_init(struct spear_pcie_gadget_config *config)
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{
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struct pcie_app_reg __iomem *app_reg = config->va_app_base;
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/*setup registers for outbound translation */
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writel(config->base, &app_reg->in0_mem_addr_start);
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writel(app_reg->in0_mem_addr_start + IN0_MEM_SIZE,
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&app_reg->in0_mem_addr_limit);
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writel(app_reg->in0_mem_addr_limit + 1, &app_reg->in1_mem_addr_start);
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writel(app_reg->in1_mem_addr_start + IN1_MEM_SIZE,
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&app_reg->in1_mem_addr_limit);
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writel(app_reg->in1_mem_addr_limit + 1, &app_reg->in_io_addr_start);
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writel(app_reg->in_io_addr_start + IN_IO_SIZE,
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&app_reg->in_io_addr_limit);
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writel(app_reg->in_io_addr_limit + 1, &app_reg->in_cfg0_addr_start);
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writel(app_reg->in_cfg0_addr_start + IN_CFG0_SIZE,
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&app_reg->in_cfg0_addr_limit);
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writel(app_reg->in_cfg0_addr_limit + 1, &app_reg->in_cfg1_addr_start);
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writel(app_reg->in_cfg1_addr_start + IN_CFG1_SIZE,
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&app_reg->in_cfg1_addr_limit);
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writel(app_reg->in_cfg1_addr_limit + 1, &app_reg->in_msg_addr_start);
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writel(app_reg->in_msg_addr_start + IN_MSG_SIZE,
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&app_reg->in_msg_addr_limit);
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writel(app_reg->in0_mem_addr_start, &app_reg->pom0_mem_addr_start);
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writel(app_reg->in1_mem_addr_start, &app_reg->pom1_mem_addr_start);
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writel(app_reg->in_io_addr_start, &app_reg->pom_io_addr_start);
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/*setup registers for inbound translation */
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/* Keep AORAM mapped at BAR0 as default */
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config->bar0_size = INBOUND_ADDR_MASK + 1;
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spear_dbi_write_reg(config, PCIE_BAR0_MASK_REG, 4, INBOUND_ADDR_MASK);
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spear_dbi_write_reg(config, PCI_BASE_ADDRESS_0, 4, 0xC);
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config->va_bar0_address = ioremap(SPEAR13XX_SYSRAM1_BASE,
|
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config->bar0_size);
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writel(SPEAR13XX_SYSRAM1_BASE, &app_reg->pim0_mem_addr_start);
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writel(0, &app_reg->pim1_mem_addr_start);
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writel(INBOUND_ADDR_MASK + 1, &app_reg->mem0_addr_offset_limit);
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writel(0x0, &app_reg->pim_io_addr_start);
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writel(0x0, &app_reg->pim_io_addr_start);
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writel(0x0, &app_reg->pim_rom_addr_start);
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writel(DEVICE_TYPE_EP | (1 << MISCTRL_EN_ID)
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| ((u32)1 << REG_TRANSLATION_ENABLE),
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&app_reg->app_ctrl_0);
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/* disable all rx interrupts */
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writel(0, &app_reg->int_mask);
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|
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/* Select INTA as default*/
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spear_dbi_write_reg(config, PCI_INTERRUPT_LINE, 1, 1);
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}
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|
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static int spear_pcie_gadget_probe(struct platform_device *pdev)
|
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{
|
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struct resource *res0, *res1;
|
|
unsigned int status = 0;
|
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int irq;
|
|
struct clk *clk;
|
|
static struct pcie_gadget_target *target;
|
|
struct spear_pcie_gadget_config *config;
|
|
struct config_item *cg_item;
|
|
struct configfs_subsystem *subsys;
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|
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target = devm_kzalloc(&pdev->dev, sizeof(*target), GFP_KERNEL);
|
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if (!target) {
|
|
dev_err(&pdev->dev, "out of memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
cg_item = &target->subsys.su_group.cg_item;
|
|
sprintf(cg_item->ci_namebuf, "pcie_gadget.%d", pdev->id);
|
|
cg_item->ci_type = &pcie_gadget_target_type;
|
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config = &target->config;
|
|
|
|
/* get resource for application registers*/
|
|
res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
config->va_app_base = devm_ioremap_resource(&pdev->dev, res0);
|
|
if (IS_ERR(config->va_app_base)) {
|
|
dev_err(&pdev->dev, "ioremap fail\n");
|
|
return PTR_ERR(config->va_app_base);
|
|
}
|
|
|
|
/* get resource for dbi registers*/
|
|
res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
config->base = (void __iomem *)res1->start;
|
|
|
|
config->va_dbi_base = devm_ioremap_resource(&pdev->dev, res1);
|
|
if (IS_ERR(config->va_dbi_base)) {
|
|
dev_err(&pdev->dev, "ioremap fail\n");
|
|
return PTR_ERR(config->va_dbi_base);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, target);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "no update irq?\n");
|
|
return irq;
|
|
}
|
|
|
|
status = devm_request_irq(&pdev->dev, irq, spear_pcie_gadget_irq,
|
|
0, pdev->name, NULL);
|
|
if (status) {
|
|
dev_err(&pdev->dev,
|
|
"pcie gadget interrupt IRQ%d already claimed\n", irq);
|
|
return status;
|
|
}
|
|
|
|
/* Register configfs hooks */
|
|
subsys = &target->subsys;
|
|
config_group_init(&subsys->su_group);
|
|
mutex_init(&subsys->su_mutex);
|
|
status = configfs_register_subsystem(subsys);
|
|
if (status)
|
|
return status;
|
|
|
|
/*
|
|
* init basic pcie application registers
|
|
* do not enable clock if it is PCIE0.Ideally , all controller should
|
|
* have been independent from others with respect to clock. But PCIE1
|
|
* and 2 depends on PCIE0.So PCIE0 clk is provided during board init.
|
|
*/
|
|
if (pdev->id == 1) {
|
|
/*
|
|
* Ideally CFG Clock should have been also enabled here. But
|
|
* it is done currently during board init routne
|
|
*/
|
|
clk = clk_get_sys("pcie1", NULL);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("%s:couldn't get clk for pcie1\n", __func__);
|
|
return PTR_ERR(clk);
|
|
}
|
|
status = clk_enable(clk);
|
|
if (status) {
|
|
pr_err("%s:couldn't enable clk for pcie1\n", __func__);
|
|
return status;
|
|
}
|
|
} else if (pdev->id == 2) {
|
|
/*
|
|
* Ideally CFG Clock should have been also enabled here. But
|
|
* it is done currently during board init routne
|
|
*/
|
|
clk = clk_get_sys("pcie2", NULL);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("%s:couldn't get clk for pcie2\n", __func__);
|
|
return PTR_ERR(clk);
|
|
}
|
|
status = clk_enable(clk);
|
|
if (status) {
|
|
pr_err("%s:couldn't enable clk for pcie2\n", __func__);
|
|
return status;
|
|
}
|
|
}
|
|
spear13xx_pcie_device_init(config);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spear_pcie_gadget_remove(struct platform_device *pdev)
|
|
{
|
|
static struct pcie_gadget_target *target;
|
|
|
|
target = platform_get_drvdata(pdev);
|
|
|
|
configfs_unregister_subsystem(&target->subsys);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void spear_pcie_gadget_shutdown(struct platform_device *pdev)
|
|
{
|
|
}
|
|
|
|
static struct platform_driver spear_pcie_gadget_driver = {
|
|
.probe = spear_pcie_gadget_probe,
|
|
.remove = spear_pcie_gadget_remove,
|
|
.shutdown = spear_pcie_gadget_shutdown,
|
|
.driver = {
|
|
.name = "pcie-gadget-spear",
|
|
.bus = &platform_bus_type
|
|
},
|
|
};
|
|
|
|
module_platform_driver(spear_pcie_gadget_driver);
|
|
|
|
MODULE_ALIAS("platform:pcie-gadget-spear");
|
|
MODULE_AUTHOR("Pratyush Anand");
|
|
MODULE_LICENSE("GPL");
|