Guttula, Suresh 0cafc82fae drm/amd/display: set backlight level limit to 1 ... This patch will work as workaround for silicon limitation related to PWM dutycycle when the backlight level goes to 0. Actually PWM value is 16 bit value and valid range from 1-65535. when ever user requested to set this PWM value to 0 which is not fall in the range, in VBIOS taken care this by limiting to 1. This patch here will do the same. Either driver or VBIOS can not pass 0 value as it is not a valid range for PWM and it will give a high PWM pulse which is not the intended behaviour as per HW constraints. Signed-off-by: suresh guttula <suresh.guttula@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-10-30 16:53:02 -05:00
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drm	drm/amd/display: set backlight level limit to 1	2018-10-30 16:53:02 -05:00
host1x
ipu-v3
vga
Makefile