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085a9f4343
Use down_read_nested() and down_write_nested() when taking the ctrl->reset_lock rw-sem, passing the number of PCIe hotplug controllers in the path to the PCI root bus as lock subclass parameter. This fixes the following false-positive lockdep report when unplugging a Lenovo X1C8 from a Lenovo 2nd gen TB3 dock: pcieport 0000:06:01.0: pciehp: Slot(1): Link Down pcieport 0000:06:01.0: pciehp: Slot(1): Card not present ============================================ WARNING: possible recursive locking detected 5.16.0-rc2+ #621 Not tainted -------------------------------------------- irq/124-pciehp/86 is trying to acquire lock: ffff8e5ac4299ef8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_check_presence+0x23/0x80 but task is already holding lock: ffff8e5ac4298af8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_ist+0xf3/0x180 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&ctrl->reset_lock); lock(&ctrl->reset_lock); *** DEADLOCK *** May be due to missing lock nesting notation 3 locks held by irq/124-pciehp/86: #0: ffff8e5ac4298af8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_ist+0xf3/0x180 #1: ffffffffa3b024e8 (pci_rescan_remove_lock){+.+.}-{3:3}, at: pciehp_unconfigure_device+0x31/0x110 #2: ffff8e5ac1ee2248 (&dev->mutex){....}-{3:3}, at: device_release_driver+0x1c/0x40 stack backtrace: CPU: 4 PID: 86 Comm: irq/124-pciehp Not tainted 5.16.0-rc2+ #621 Hardware name: LENOVO 20U90SIT19/20U90SIT19, BIOS N2WET30W (1.20 ) 08/26/2021 Call Trace: <TASK> dump_stack_lvl+0x59/0x73 __lock_acquire.cold+0xc5/0x2c6 lock_acquire+0xb5/0x2b0 down_read+0x3e/0x50 pciehp_check_presence+0x23/0x80 pciehp_runtime_resume+0x5c/0xa0 device_for_each_child+0x45/0x70 pcie_port_device_runtime_resume+0x20/0x30 pci_pm_runtime_resume+0xa7/0xc0 __rpm_callback+0x41/0x110 rpm_callback+0x59/0x70 rpm_resume+0x512/0x7b0 __pm_runtime_resume+0x4a/0x90 __device_release_driver+0x28/0x240 device_release_driver+0x26/0x40 pci_stop_bus_device+0x68/0x90 pci_stop_bus_device+0x2c/0x90 pci_stop_and_remove_bus_device+0xe/0x20 pciehp_unconfigure_device+0x6c/0x110 pciehp_disable_slot+0x5b/0xe0 pciehp_handle_presence_or_link_change+0xc3/0x2f0 pciehp_ist+0x179/0x180 This lockdep warning is triggered because with Thunderbolt, hotplug ports are nested. When removing multiple devices in a daisy-chain, each hotplug port's reset_lock may be acquired recursively. It's never the same lock, so the lockdep splat is a false positive. Because locks at the same hierarchy level are never acquired recursively, a per-level lockdep class is sufficient to fix the lockdep warning. The choice to use one lockdep subclass per pcie-hotplug controller in the path to the root-bus was made to conserve class keys because their number is limited and the complexity grows quadratically with number of keys according to Documentation/locking/lockdep-design.rst. Link: https://lore.kernel.org/linux-pci/20190402021933.GA2966@mit.edu/ Link: https://lore.kernel.org/linux-pci/de684a28-9038-8fc6-27ca-3f6f2f6400d7@redhat.com/ Link: https://lore.kernel.org/r/20211217141709.379663-1-hdegoede@redhat.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=208855 Reported-by: "Theodore Ts'o" <tytso@mit.edu> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lukas Wunner <lukas@wunner.de> Cc: stable@vger.kernel.org
207 lines
8.2 KiB
C
207 lines
8.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* PCI Express Hot Plug Controller Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
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*
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*/
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#ifndef _PCIEHP_H
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#define _PCIEHP_H
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/pci_hotplug.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/rwsem.h>
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#include <linux/workqueue.h>
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#include "../pcie/portdrv.h"
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extern bool pciehp_poll_mode;
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extern int pciehp_poll_time;
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/*
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* Set CONFIG_DYNAMIC_DEBUG=y and boot with 'dyndbg="file pciehp* +p"' to
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* enable debug messages.
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*/
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#define ctrl_dbg(ctrl, format, arg...) \
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pci_dbg(ctrl->pcie->port, format, ## arg)
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#define ctrl_err(ctrl, format, arg...) \
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pci_err(ctrl->pcie->port, format, ## arg)
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#define ctrl_info(ctrl, format, arg...) \
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pci_info(ctrl->pcie->port, format, ## arg)
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#define ctrl_warn(ctrl, format, arg...) \
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pci_warn(ctrl->pcie->port, format, ## arg)
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#define SLOT_NAME_SIZE 10
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/**
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* struct controller - PCIe hotplug controller
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* @pcie: pointer to the controller's PCIe port service device
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* @slot_cap: cached copy of the Slot Capabilities register
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* @inband_presence_disabled: In-Band Presence Detect Disable supported by
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* controller and disabled per spec recommendation (PCIe r5.0, appendix I
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* implementation note)
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* @slot_ctrl: cached copy of the Slot Control register
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* @ctrl_lock: serializes writes to the Slot Control register
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* @cmd_started: jiffies when the Slot Control register was last written;
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* the next write is allowed 1 second later, absent a Command Completed
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* interrupt (PCIe r4.0, sec 6.7.3.2)
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* @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
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* on reception of a Command Completed event
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* @queue: wait queue to wake up on reception of a Command Completed event,
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* used for synchronous writes to the Slot Control register
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* @pending_events: used by the IRQ handler to save events retrieved from the
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* Slot Status register for later consumption by the IRQ thread
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* @notification_enabled: whether the IRQ was requested successfully
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* @power_fault_detected: whether a power fault was detected by the hardware
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* that has not yet been cleared by the user
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* @poll_thread: thread to poll for slot events if no IRQ is available,
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* enabled with pciehp_poll_mode module parameter
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* @state: current state machine position
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* @state_lock: protects reads and writes of @state;
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* protects scheduling, execution and cancellation of @button_work
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* @button_work: work item to turn the slot on or off after 5 seconds
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* in response to an Attention Button press
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* @hotplug_slot: structure registered with the PCI hotplug core
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* @reset_lock: prevents access to the Data Link Layer Link Active bit in the
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* Link Status register and to the Presence Detect State bit in the Slot
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* Status register during a slot reset which may cause them to flap
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* @depth: Number of additional hotplug ports in the path to the root bus,
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* used as lock subclass for @reset_lock
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* @ist_running: flag to keep user request waiting while IRQ thread is running
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* @request_result: result of last user request submitted to the IRQ thread
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* @requester: wait queue to wake up on completion of user request,
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* used for synchronous slot enable/disable request via sysfs
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*
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* PCIe hotplug has a 1:1 relationship between controller and slot, hence
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* unlike other drivers, the two aren't represented by separate structures.
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*/
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struct controller {
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struct pcie_device *pcie;
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u32 slot_cap; /* capabilities and quirks */
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unsigned int inband_presence_disabled:1;
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u16 slot_ctrl; /* control register access */
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struct mutex ctrl_lock;
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unsigned long cmd_started;
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unsigned int cmd_busy:1;
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wait_queue_head_t queue;
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atomic_t pending_events; /* event handling */
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unsigned int notification_enabled:1;
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unsigned int power_fault_detected;
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struct task_struct *poll_thread;
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u8 state; /* state machine */
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struct mutex state_lock;
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struct delayed_work button_work;
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struct hotplug_slot hotplug_slot; /* hotplug core interface */
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struct rw_semaphore reset_lock;
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unsigned int depth;
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unsigned int ist_running;
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int request_result;
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wait_queue_head_t requester;
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};
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/**
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* DOC: Slot state
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*
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* @OFF_STATE: slot is powered off, no subordinate devices are enumerated
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* @BLINKINGON_STATE: slot will be powered on after the 5 second delay,
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* Power Indicator is blinking
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* @BLINKINGOFF_STATE: slot will be powered off after the 5 second delay,
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* Power Indicator is blinking
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* @POWERON_STATE: slot is currently powering on
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* @POWEROFF_STATE: slot is currently powering off
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* @ON_STATE: slot is powered on, subordinate devices have been enumerated
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*/
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#define OFF_STATE 0
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#define BLINKINGON_STATE 1
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#define BLINKINGOFF_STATE 2
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#define POWERON_STATE 3
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#define POWEROFF_STATE 4
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#define ON_STATE 5
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/**
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* DOC: Flags to request an action from the IRQ thread
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*
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* These are stored together with events read from the Slot Status register,
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* hence must be greater than its 16-bit width.
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*
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* %DISABLE_SLOT: Disable the slot in response to a user request via sysfs or
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* an Attention Button press after the 5 second delay
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* %RERUN_ISR: Used by the IRQ handler to inform the IRQ thread that the
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* hotplug port was inaccessible when the interrupt occurred, requiring
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* that the IRQ handler is rerun by the IRQ thread after it has made the
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* hotplug port accessible by runtime resuming its parents to D0
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*/
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#define DISABLE_SLOT (1 << 16)
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#define RERUN_ISR (1 << 17)
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#define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
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#define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
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#define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
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#define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
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#define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
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#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
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#define PSN(ctrl) (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19)
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void pciehp_request(struct controller *ctrl, int action);
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void pciehp_handle_button_press(struct controller *ctrl);
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void pciehp_handle_disable_request(struct controller *ctrl);
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void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events);
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int pciehp_configure_device(struct controller *ctrl);
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void pciehp_unconfigure_device(struct controller *ctrl, bool presence);
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void pciehp_queue_pushbutton_work(struct work_struct *work);
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struct controller *pcie_init(struct pcie_device *dev);
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int pcie_init_notification(struct controller *ctrl);
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void pcie_shutdown_notification(struct controller *ctrl);
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void pcie_clear_hotplug_events(struct controller *ctrl);
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void pcie_enable_interrupt(struct controller *ctrl);
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void pcie_disable_interrupt(struct controller *ctrl);
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int pciehp_power_on_slot(struct controller *ctrl);
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void pciehp_power_off_slot(struct controller *ctrl);
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void pciehp_get_power_status(struct controller *ctrl, u8 *status);
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#define INDICATOR_NOOP -1 /* Leave indicator unchanged */
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void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn);
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void pciehp_get_latch_status(struct controller *ctrl, u8 *status);
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int pciehp_query_power_fault(struct controller *ctrl);
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int pciehp_card_present(struct controller *ctrl);
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int pciehp_card_present_or_link_active(struct controller *ctrl);
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int pciehp_check_link_status(struct controller *ctrl);
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int pciehp_check_link_active(struct controller *ctrl);
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void pciehp_release_ctrl(struct controller *ctrl);
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int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot);
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int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot);
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int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe);
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int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status);
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int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status);
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int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status);
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int pciehp_slot_reset(struct pcie_device *dev);
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static inline const char *slot_name(struct controller *ctrl)
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{
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return hotplug_slot_name(&ctrl->hotplug_slot);
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}
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static inline struct controller *to_ctrl(struct hotplug_slot *hotplug_slot)
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{
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return container_of(hotplug_slot, struct controller, hotplug_slot);
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}
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#endif /* _PCIEHP_H */
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