Suzuki K Poulose e4e7f67cc1 arm64: errata: Add detection for TRBE overwrite in FILL mode ... commit b9d216fcef upstream Arm Neoverse-N2 and the Cortex-A710 cores are affected by a CPU erratum where the TRBE will overwrite the trace buffer in FILL mode. The TRBE doesn't stop (as expected in FILL mode) when it reaches the limit and wraps to the base to continue writing upto 3 cache lines. This will overwrite any trace that was written previously. Add the Neoverse-N2 erratum(#2139208) and Cortex-A710 erratum (#2119858) to the detection logic. This will be used by the TRBE driver in later patches to work around the issue. The detection has been kept with the core arm64 errata framework list to make sure : - We don't duplicate the framework in TRBE driver - The errata detection is advertised like the rest of the CPU errata. Note that the Kconfig entries are not fully active until the TRBE driver implements the work around. Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> cc: Leo Yan <leo.yan@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20211019163153.3692640-3-suzuki.poulose@arm.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2023-07-23 13:47:48 +02:00
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acpi_object_usage.rst	Documentation: arm64/acpi : clarify arm64 support of IBFT	2021-03-22 12:43:20 +00:00
amu.rst	Documentation: Chinese translation of Documentation/arm64/amu.rst	2020-09-28 15:24:24 -06:00
arm-acpi.rst	arm64: Replace HTTP links with HTTPS ones	2020-07-23 14:04:37 -06:00
asymmetric-32bit.rst	Documentation: arm64: describe asymmetric 32-bit support	2021-08-20 12:33:07 +02:00
booting.rst	arm64: Document the requirement for SCR_EL3.HCE	2021-08-24 16:44:23 +01:00
cpu-feature-registers.rst	arm64: cpufeature: add HWCAP for FEAT_RPRES	2022-03-11 12:22:33 +01:00
elf_hwcaps.rst	arm64: cpufeature: add HWCAP for FEAT_RPRES	2022-03-11 12:22:33 +01:00
features.rst	docs: archis: add a per-architecture features list	2020-12-03 15:10:15 -07:00
hugetlbpage.rst	Documentation: Chinese translation of Documentation/arm64/hugetlbpage.rst	2020-10-21 15:15:17 -06:00
index.rst	Documentation: arm64: describe asymmetric 32-bit support	2021-08-20 12:33:07 +02:00
kasan-offsets.sh	arm64: mm: extend linear region for 52-bit VA configurations	2020-11-09 17:15:37 +00:00
legacy_instructions.rst
memory-tagging-extension.rst	Documentation: document the preferred tag checking mode feature	2021-07-28 18:39:26 +01:00
memory.rst	ARM:	2020-12-20 10:44:05 -08:00
perf.rst	Documentation: Chinese translation of Documentation/arm64/perf.rst	2020-11-13 15:21:38 -07:00
pointer-authentication.rst	arm64: Introduce prctl(PR_PAC_{SET,GET}_ENABLED_KEYS)	2021-04-13 17:31:44 +01:00
silicon-errata.rst	arm64: errata: Add detection for TRBE overwrite in FILL mode	2023-07-23 13:47:48 +02:00
sve.rst	It's been a busy cycle for documentation - hopefully the busiest for a	2020-08-04 22:47:54 -07:00
tagged-address-abi.rst	userfaultfd: do not untag user pointers	2021-07-23 17:43:28 -07:00
tagged-pointers.rst	arm64: expose FAR_EL1 tag bits in siginfo	2020-11-23 18:17:39 +00:00