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![Marek Szyprowski](/assets/img/avatar_default.png)
Support for Exynos5420/5422/5800 SoCs requires MCPM to properly boot all CPU cores on all currectly supported platforms: Peach Pit (Exynos5420), Odroid XU3/XU3lite/XU4/HC1 (Exynos5422) and Peach Pi (Exynos5800). Without it some CPU cores fail to come online. Remove then the ability to disable MCPM and make it mandatory when Exynos542x/5800 support is enabled. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
701 lines
17 KiB
C
701 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
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// http://www.samsung.com
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//
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// EXYNOS - Suspend support
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//
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// Based on arch/arm/mach-s3c2410/pm.c
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// Copyright (c) 2006 Simtec Electronics
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// Ben Dooks <ben@simtec.co.uk>
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/syscore_ops.h>
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#include <linux/cpu_pm.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/err.h>
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#include <linux/regulator/machine.h>
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#include <linux/soc/samsung/exynos-pmu.h>
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#include <linux/soc/samsung/exynos-regs-pmu.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/firmware.h>
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#include <asm/mcpm.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include "common.h"
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#include "smc.h"
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#define REG_TABLE_END (-1U)
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#define EXYNOS5420_CPU_STATE 0x28
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/**
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* struct exynos_wkup_irq - PMU IRQ to mask mapping
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* @hwirq: Hardware IRQ signal of the PMU
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* @mask: Mask in PMU wake-up mask register
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*/
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struct exynos_wkup_irq {
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unsigned int hwirq;
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u32 mask;
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};
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struct exynos_pm_data {
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const struct exynos_wkup_irq *wkup_irq;
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unsigned int wake_disable_mask;
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void (*pm_prepare)(void);
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void (*pm_resume_prepare)(void);
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void (*pm_resume)(void);
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int (*pm_suspend)(void);
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int (*cpu_suspend)(unsigned long);
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};
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/* Used only on Exynos542x/5800 */
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struct exynos_pm_state {
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int cpu_state;
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unsigned int pmu_spare3;
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void __iomem *sysram_base;
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phys_addr_t sysram_phys;
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bool secure_firmware;
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};
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static const struct exynos_pm_data *pm_data __ro_after_init;
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static struct exynos_pm_state pm_state;
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/*
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* GIC wake-up support
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*/
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static u32 exynos_irqwake_intmask = 0xffffffff;
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static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
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{ 73, BIT(1) }, /* RTC alarm */
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{ 74, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
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{ 44, BIT(1) }, /* RTC alarm */
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{ 45, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
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{ 43, BIT(1) }, /* RTC alarm */
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{ 44, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static u32 exynos_read_eint_wakeup_mask(void)
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{
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return pmu_raw_readl(EXYNOS_EINT_WAKEUP_MASK);
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}
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static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
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{
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const struct exynos_wkup_irq *wkup_irq;
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if (!pm_data->wkup_irq)
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return -ENOENT;
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wkup_irq = pm_data->wkup_irq;
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while (wkup_irq->mask) {
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if (wkup_irq->hwirq == data->hwirq) {
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if (!state)
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exynos_irqwake_intmask |= wkup_irq->mask;
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else
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exynos_irqwake_intmask &= ~wkup_irq->mask;
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return 0;
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}
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++wkup_irq;
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}
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return -ENOENT;
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}
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static struct irq_chip exynos_pmu_chip = {
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.name = "PMU",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_wake = exynos_irq_set_wake,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int exynos_pmu_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2];
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return 0;
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}
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return -EINVAL;
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}
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static int exynos_pmu_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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int i;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = fwspec->param[1];
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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&exynos_pmu_chip, NULL);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops exynos_pmu_domain_ops = {
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.translate = exynos_pmu_domain_translate,
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.alloc = exynos_pmu_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int __init exynos_pmu_irq_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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if (!parent) {
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pr_err("%pOF: no parent, giving up\n", node);
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%pOF: unable to obtain parent domain\n", node);
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return -ENXIO;
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}
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pmu_base_addr = of_iomap(node, 0);
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if (!pmu_base_addr) {
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pr_err("%pOF: failed to find exynos pmu register\n", node);
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return -ENOMEM;
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}
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domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
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node, &exynos_pmu_domain_ops,
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NULL);
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if (!domain) {
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iounmap(pmu_base_addr);
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pmu_base_addr = NULL;
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return -ENOMEM;
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}
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/*
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* Clear the OF_POPULATED flag set in of_irq_init so that
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* later the Exynos PMU platform device won't be skipped.
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*/
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of_node_clear_flag(node, OF_POPULATED);
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return 0;
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}
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#define EXYNOS_PMU_IRQ(symbol, name) IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
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EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
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EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
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EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
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EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
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EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
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static int exynos_cpu_do_idle(void)
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{
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/* issue the standby signal into the pm unit. */
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cpu_do_idle();
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pr_info("Failed to suspend the system\n");
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return 1; /* Aborting suspend */
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}
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static void exynos_flush_cache_all(void)
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{
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flush_cache_all();
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outer_flush_all();
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}
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static int exynos_cpu_suspend(unsigned long arg)
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{
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exynos_flush_cache_all();
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return exynos_cpu_do_idle();
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}
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static int exynos3250_cpu_suspend(unsigned long arg)
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{
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flush_cache_all();
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return exynos_cpu_do_idle();
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}
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static int exynos5420_cpu_suspend(unsigned long arg)
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{
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/* MCPM works with HW CPU identifiers */
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unsigned int mpidr = read_cpuid_mpidr();
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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if (IS_ENABLED(CONFIG_MCPM)) {
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mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
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mcpm_cpu_suspend();
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}
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pr_info("Failed to suspend the system\n");
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/* return value != 0 means failure */
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return 1;
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}
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static void exynos_pm_set_wakeup_mask(void)
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{
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/*
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* Set wake-up mask registers
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* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
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*/
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pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
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}
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static void exynos_pm_enter_sleep_mode(void)
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{
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/* Set value of power down register for sleep mode */
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exynos_sys_powerdown_conf(SYS_SLEEP);
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pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
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}
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static void exynos_pm_prepare(void)
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{
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exynos_set_delayed_reset_assertion(false);
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos3250_pm_prepare(void)
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{
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unsigned int tmp;
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
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tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
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pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos5420_pm_prepare(void)
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{
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unsigned int tmp;
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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pm_state.pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
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/*
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* The cpu state needs to be saved and restored so that the
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* secondary CPUs will enter low power start. Though the U-Boot
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* is setting the cpu state with low power flag, the kernel
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* needs to restore it back in case, the primary cpu fails to
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* suspend for any reason.
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*/
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pm_state.cpu_state = readl_relaxed(pm_state.sysram_base +
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EXYNOS5420_CPU_STATE);
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writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
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if (pm_state.secure_firmware)
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exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(pm_state.sysram_phys +
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EXYNOS5420_CPU_STATE),
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0, 0);
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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if (IS_ENABLED(CONFIG_MCPM))
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pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
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tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
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tmp &= ~EXYNOS_L2_USE_RETENTION;
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pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
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tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
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tmp |= EXYNOS5420_UFS;
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pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
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tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
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tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
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pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
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tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
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tmp |= EXYNOS5420_EMULATION;
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pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
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tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
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tmp |= EXYNOS5420_EMULATION;
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pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
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}
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static int exynos_pm_suspend(void)
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{
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exynos_pm_central_suspend();
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/* Setting SEQ_OPTION register */
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pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
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S5P_CENTRAL_SEQ_OPTION);
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_save_register();
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return 0;
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}
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static int exynos5420_pm_suspend(void)
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{
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u32 this_cluster;
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exynos_pm_central_suspend();
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/* Setting SEQ_OPTION register */
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this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
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if (!this_cluster)
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pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
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S5P_CENTRAL_SEQ_OPTION);
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else
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pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
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S5P_CENTRAL_SEQ_OPTION);
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return 0;
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}
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static void exynos_pm_resume(void)
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{
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u32 cpuid = read_cpuid_part();
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if (exynos_pm_central_resume())
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goto early_wakeup;
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if (cpuid == ARM_CPU_PART_CORTEX_A9)
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exynos_scu_enable();
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if (call_firmware_op(resume) == -ENOSYS
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&& cpuid == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_restore_register();
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early_wakeup:
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/* Clear SLEEP mode set in INFORM1 */
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pmu_raw_writel(0x0, S5P_INFORM1);
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exynos_set_delayed_reset_assertion(true);
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}
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static void exynos3250_pm_resume(void)
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{
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u32 cpuid = read_cpuid_part();
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if (exynos_pm_central_resume())
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goto early_wakeup;
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pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
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if (call_firmware_op(resume) == -ENOSYS
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&& cpuid == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_restore_register();
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early_wakeup:
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/* Clear SLEEP mode set in INFORM1 */
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pmu_raw_writel(0x0, S5P_INFORM1);
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}
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static void exynos5420_prepare_pm_resume(void)
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{
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unsigned int mpidr, cluster;
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mpidr = read_cpuid_mpidr();
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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if (IS_ENABLED(CONFIG_MCPM))
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WARN_ON(mcpm_cpu_powered_up());
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if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
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/*
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* When system is resumed on the LITTLE/KFC core (cluster 1),
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* the DSCR is not properly updated until the power is turned
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* on also for the cluster 0. Enable it for a while to
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* propagate the SPNIDEN and SPIDEN signals from Secure JTAG
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* block and avoid undefined instruction issue on CP14 reset.
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*/
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pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
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EXYNOS_COMMON_CONFIGURATION(0));
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pmu_raw_writel(0,
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EXYNOS_COMMON_CONFIGURATION(0));
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}
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}
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static void exynos5420_pm_resume(void)
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{
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unsigned long tmp;
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|
|
|
/* Restore the CPU0 low power state register */
|
|
tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
|
|
pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
|
|
EXYNOS5_ARM_CORE0_SYS_PWR_REG);
|
|
|
|
/* Restore the sysram cpu state register */
|
|
writel_relaxed(pm_state.cpu_state,
|
|
pm_state.sysram_base + EXYNOS5420_CPU_STATE);
|
|
if (pm_state.secure_firmware)
|
|
exynos_smc(SMC_CMD_REG,
|
|
SMC_REG_ID_SFR_W(pm_state.sysram_phys +
|
|
EXYNOS5420_CPU_STATE),
|
|
EXYNOS_AFTR_MAGIC, 0);
|
|
|
|
pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
|
|
S5P_CENTRAL_SEQ_OPTION);
|
|
|
|
if (exynos_pm_central_resume())
|
|
goto early_wakeup;
|
|
|
|
pmu_raw_writel(pm_state.pmu_spare3, S5P_PMU_SPARE3);
|
|
|
|
early_wakeup:
|
|
|
|
tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
|
|
tmp &= ~EXYNOS5420_UFS;
|
|
pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
|
|
|
|
tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
|
|
tmp &= ~EXYNOS5420_EMULATION;
|
|
pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
|
|
|
|
tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
|
|
tmp &= ~EXYNOS5420_EMULATION;
|
|
pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
|
|
|
|
/* Clear SLEEP mode set in INFORM1 */
|
|
pmu_raw_writel(0x0, S5P_INFORM1);
|
|
}
|
|
|
|
/*
|
|
* Suspend Ops
|
|
*/
|
|
|
|
static int exynos_suspend_enter(suspend_state_t state)
|
|
{
|
|
u32 eint_wakeup_mask = exynos_read_eint_wakeup_mask();
|
|
int ret;
|
|
|
|
pr_debug("%s: suspending the system...\n", __func__);
|
|
|
|
pr_debug("%s: wakeup masks: %08x,%08x\n", __func__,
|
|
exynos_irqwake_intmask, eint_wakeup_mask);
|
|
|
|
if (exynos_irqwake_intmask == -1U
|
|
&& eint_wakeup_mask == EXYNOS_EINT_WAKEUP_MASK_DISABLED) {
|
|
pr_err("%s: No wake-up sources!\n", __func__);
|
|
pr_err("%s: Aborting sleep\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (pm_data->pm_prepare)
|
|
pm_data->pm_prepare();
|
|
flush_cache_all();
|
|
|
|
ret = call_firmware_op(suspend);
|
|
if (ret == -ENOSYS)
|
|
ret = cpu_suspend(0, pm_data->cpu_suspend);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (pm_data->pm_resume_prepare)
|
|
pm_data->pm_resume_prepare();
|
|
|
|
pr_debug("%s: wakeup stat: %08x\n", __func__,
|
|
pmu_raw_readl(S5P_WAKEUP_STAT));
|
|
|
|
pr_debug("%s: resuming the system...\n", __func__);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_suspend_prepare(void)
|
|
{
|
|
int ret;
|
|
|
|
/*
|
|
* REVISIT: It would be better if struct platform_suspend_ops
|
|
* .prepare handler get the suspend_state_t as a parameter to
|
|
* avoid hard-coding the suspend to mem state. It's safe to do
|
|
* it now only because the suspend_valid_only_mem function is
|
|
* used as the .valid callback used to check if a given state
|
|
* is supported by the platform anyways.
|
|
*/
|
|
ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
|
|
if (ret) {
|
|
pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void exynos_suspend_finish(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = regulator_suspend_finish();
|
|
if (ret)
|
|
pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
|
|
}
|
|
|
|
static const struct platform_suspend_ops exynos_suspend_ops = {
|
|
.enter = exynos_suspend_enter,
|
|
.prepare = exynos_suspend_prepare,
|
|
.finish = exynos_suspend_finish,
|
|
.valid = suspend_valid_only_mem,
|
|
};
|
|
|
|
static const struct exynos_pm_data exynos3250_pm_data = {
|
|
.wkup_irq = exynos3250_wkup_irq,
|
|
.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
|
|
.pm_suspend = exynos_pm_suspend,
|
|
.pm_resume = exynos3250_pm_resume,
|
|
.pm_prepare = exynos3250_pm_prepare,
|
|
.cpu_suspend = exynos3250_cpu_suspend,
|
|
};
|
|
|
|
static const struct exynos_pm_data exynos4_pm_data = {
|
|
.wkup_irq = exynos4_wkup_irq,
|
|
.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
|
|
.pm_suspend = exynos_pm_suspend,
|
|
.pm_resume = exynos_pm_resume,
|
|
.pm_prepare = exynos_pm_prepare,
|
|
.cpu_suspend = exynos_cpu_suspend,
|
|
};
|
|
|
|
static const struct exynos_pm_data exynos5250_pm_data = {
|
|
.wkup_irq = exynos5250_wkup_irq,
|
|
.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
|
|
.pm_suspend = exynos_pm_suspend,
|
|
.pm_resume = exynos_pm_resume,
|
|
.pm_prepare = exynos_pm_prepare,
|
|
.cpu_suspend = exynos_cpu_suspend,
|
|
};
|
|
|
|
static const struct exynos_pm_data exynos5420_pm_data = {
|
|
.wkup_irq = exynos5250_wkup_irq,
|
|
.wake_disable_mask = (0x7F << 7) | (0x1F << 1),
|
|
.pm_resume_prepare = exynos5420_prepare_pm_resume,
|
|
.pm_resume = exynos5420_pm_resume,
|
|
.pm_suspend = exynos5420_pm_suspend,
|
|
.pm_prepare = exynos5420_pm_prepare,
|
|
.cpu_suspend = exynos5420_cpu_suspend,
|
|
};
|
|
|
|
static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
|
|
{
|
|
.compatible = "samsung,exynos3250-pmu",
|
|
.data = &exynos3250_pm_data,
|
|
}, {
|
|
.compatible = "samsung,exynos4210-pmu",
|
|
.data = &exynos4_pm_data,
|
|
}, {
|
|
.compatible = "samsung,exynos4412-pmu",
|
|
.data = &exynos4_pm_data,
|
|
}, {
|
|
.compatible = "samsung,exynos5250-pmu",
|
|
.data = &exynos5250_pm_data,
|
|
}, {
|
|
.compatible = "samsung,exynos5420-pmu",
|
|
.data = &exynos5420_pm_data,
|
|
},
|
|
{ /*sentinel*/ },
|
|
};
|
|
|
|
static struct syscore_ops exynos_pm_syscore_ops;
|
|
|
|
void __init exynos_pm_init(void)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct device_node *np;
|
|
u32 tmp;
|
|
|
|
np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
|
|
if (!np) {
|
|
pr_err("Failed to find PMU node\n");
|
|
return;
|
|
}
|
|
|
|
if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
|
|
pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
|
|
of_node_put(np);
|
|
return;
|
|
}
|
|
of_node_put(np);
|
|
|
|
pm_data = (const struct exynos_pm_data *) match->data;
|
|
|
|
/* All wakeup disable */
|
|
tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
|
|
tmp |= pm_data->wake_disable_mask;
|
|
pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
|
|
|
|
exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
|
|
exynos_pm_syscore_ops.resume = pm_data->pm_resume;
|
|
|
|
register_syscore_ops(&exynos_pm_syscore_ops);
|
|
suspend_set_ops(&exynos_suspend_ops);
|
|
|
|
/*
|
|
* Applicable as of now only to Exynos542x. If booted under secure
|
|
* firmware, the non-secure region of sysram should be used.
|
|
*/
|
|
if (exynos_secure_firmware_available()) {
|
|
pm_state.sysram_phys = sysram_base_phys;
|
|
pm_state.sysram_base = sysram_ns_base_addr;
|
|
pm_state.secure_firmware = true;
|
|
} else {
|
|
pm_state.sysram_base = sysram_base_addr;
|
|
}
|
|
}
|