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Add SPDX identifiers to files under sti directory Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Vincent Abriou <vincent.abriou@st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171206112947.9569-2-benjamin.gaignard@st.com
211 lines
5.7 KiB
C
211 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics SA 2014
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* Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
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*/
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#include "sti_hdmi_tx3g4c28phy.h"
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#define HDMI_SRZ_CFG 0x504
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#define HDMI_SRZ_PLL_CFG 0x510
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#define HDMI_SRZ_ICNTL 0x518
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#define HDMI_SRZ_CALCODE_EXT 0x520
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#define HDMI_SRZ_CFG_EN BIT(0)
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#define HDMI_SRZ_CFG_DISABLE_BYPASS_SINK_CURRENT BIT(1)
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#define HDMI_SRZ_CFG_EXTERNAL_DATA BIT(16)
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#define HDMI_SRZ_CFG_RBIAS_EXT BIT(17)
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#define HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION BIT(18)
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#define HDMI_SRZ_CFG_EN_BIASRES_DETECTION BIT(19)
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#define HDMI_SRZ_CFG_EN_SRC_TERMINATION BIT(24)
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#define HDMI_SRZ_CFG_INTERNAL_MASK (HDMI_SRZ_CFG_EN | \
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HDMI_SRZ_CFG_DISABLE_BYPASS_SINK_CURRENT | \
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HDMI_SRZ_CFG_EXTERNAL_DATA | \
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HDMI_SRZ_CFG_RBIAS_EXT | \
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HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION | \
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HDMI_SRZ_CFG_EN_BIASRES_DETECTION | \
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HDMI_SRZ_CFG_EN_SRC_TERMINATION)
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#define PLL_CFG_EN BIT(0)
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#define PLL_CFG_NDIV_SHIFT (8)
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#define PLL_CFG_IDF_SHIFT (16)
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#define PLL_CFG_ODF_SHIFT (24)
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#define ODF_DIV_1 (0)
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#define ODF_DIV_2 (1)
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#define ODF_DIV_4 (2)
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#define ODF_DIV_8 (3)
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#define HDMI_TIMEOUT_PLL_LOCK 50 /*milliseconds */
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struct plldividers_s {
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uint32_t min;
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uint32_t max;
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uint32_t idf;
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uint32_t odf;
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};
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/*
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* Functional specification recommended values
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*/
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#define NB_PLL_MODE 5
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static struct plldividers_s plldividers[NB_PLL_MODE] = {
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{0, 20000000, 1, ODF_DIV_8},
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{20000000, 42500000, 2, ODF_DIV_8},
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{42500000, 85000000, 4, ODF_DIV_4},
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{85000000, 170000000, 8, ODF_DIV_2},
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{170000000, 340000000, 16, ODF_DIV_1}
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};
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#define NB_HDMI_PHY_CONFIG 2
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static struct hdmi_phy_config hdmiphy_config[NB_HDMI_PHY_CONFIG] = {
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{0, 250000000, {0x0, 0x0, 0x0, 0x0} },
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{250000000, 300000000, {0x1110, 0x0, 0x0, 0x0} },
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};
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/**
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* Start hdmi phy macro cell tx3g4c28
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*
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* @hdmi: pointer on the hdmi internal structure
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*
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* Return false if an error occur
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*/
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static bool sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi)
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{
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u32 ckpxpll = hdmi->mode.clock * 1000;
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u32 val, tmdsck, idf, odf, pllctrl = 0;
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bool foundplldivides = false;
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int i;
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DRM_DEBUG_DRIVER("ckpxpll = %dHz\n", ckpxpll);
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for (i = 0; i < NB_PLL_MODE; i++) {
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if (ckpxpll >= plldividers[i].min &&
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ckpxpll < plldividers[i].max) {
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idf = plldividers[i].idf;
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odf = plldividers[i].odf;
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foundplldivides = true;
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break;
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}
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}
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if (!foundplldivides) {
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DRM_ERROR("input TMDS clock speed (%d) not supported\n",
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ckpxpll);
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goto err;
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}
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/* Assuming no pixel repetition and 24bits color */
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tmdsck = ckpxpll;
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pllctrl |= 40 << PLL_CFG_NDIV_SHIFT;
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if (tmdsck > 340000000) {
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DRM_ERROR("output TMDS clock (%d) out of range\n", tmdsck);
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goto err;
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}
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pllctrl |= idf << PLL_CFG_IDF_SHIFT;
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pllctrl |= odf << PLL_CFG_ODF_SHIFT;
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/*
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* Configure and power up the PHY PLL
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*/
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hdmi->event_received = false;
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DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl);
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hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG);
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/* wait PLL interrupt */
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wait_event_interruptible_timeout(hdmi->wait_event,
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hdmi->event_received == true,
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msecs_to_jiffies
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(HDMI_TIMEOUT_PLL_LOCK));
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if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) {
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DRM_ERROR("hdmi phy pll not locked\n");
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goto err;
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}
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DRM_DEBUG_DRIVER("got PHY PLL Lock\n");
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val = (HDMI_SRZ_CFG_EN |
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HDMI_SRZ_CFG_EXTERNAL_DATA |
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HDMI_SRZ_CFG_EN_BIASRES_DETECTION |
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HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION);
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if (tmdsck > 165000000)
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val |= HDMI_SRZ_CFG_EN_SRC_TERMINATION;
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/*
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* To configure the source termination and pre-emphasis appropriately
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* for different high speed TMDS clock frequencies a phy configuration
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* table must be provided, tailored to the SoC and board combination.
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*/
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for (i = 0; i < NB_HDMI_PHY_CONFIG; i++) {
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if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) &&
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(hdmiphy_config[i].max_tmds_freq >= tmdsck)) {
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val |= (hdmiphy_config[i].config[0]
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& ~HDMI_SRZ_CFG_INTERNAL_MASK);
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hdmi_write(hdmi, val, HDMI_SRZ_CFG);
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val = hdmiphy_config[i].config[1];
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hdmi_write(hdmi, val, HDMI_SRZ_ICNTL);
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val = hdmiphy_config[i].config[2];
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hdmi_write(hdmi, val, HDMI_SRZ_CALCODE_EXT);
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DRM_DEBUG_DRIVER("serializer cfg 0x%x 0x%x 0x%x\n",
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hdmiphy_config[i].config[0],
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hdmiphy_config[i].config[1],
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hdmiphy_config[i].config[2]);
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return true;
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}
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}
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/*
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* Default, power up the serializer with no pre-emphasis or
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* output swing correction
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*/
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hdmi_write(hdmi, val, HDMI_SRZ_CFG);
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hdmi_write(hdmi, 0x0, HDMI_SRZ_ICNTL);
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hdmi_write(hdmi, 0x0, HDMI_SRZ_CALCODE_EXT);
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return true;
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err:
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return false;
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}
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/**
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* Stop hdmi phy macro cell tx3g4c28
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*
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* @hdmi: pointer on the hdmi internal structure
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*/
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static void sti_hdmi_tx3g4c28phy_stop(struct sti_hdmi *hdmi)
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{
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int val = 0;
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DRM_DEBUG_DRIVER("\n");
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hdmi->event_received = false;
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val = HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION;
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val |= HDMI_SRZ_CFG_EN_BIASRES_DETECTION;
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hdmi_write(hdmi, val, HDMI_SRZ_CFG);
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hdmi_write(hdmi, 0, HDMI_SRZ_PLL_CFG);
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/* wait PLL interrupt */
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wait_event_interruptible_timeout(hdmi->wait_event,
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hdmi->event_received == true,
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msecs_to_jiffies
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(HDMI_TIMEOUT_PLL_LOCK));
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if (hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK)
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DRM_ERROR("hdmi phy pll not well disabled\n");
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}
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struct hdmi_phy_ops tx3g4c28phy_ops = {
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.start = sti_hdmi_tx3g4c28phy_start,
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.stop = sti_hdmi_tx3g4c28phy_stop,
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};
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