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013de2d667
This patch adds files related to memory management and here is our memory-layout: Fixmap : 0xffc02000 – 0xfffff000 (4 MB - 12KB) Pkmap : 0xff800000 – 0xffc00000 (4 MB) Vmalloc : 0xf0200000 – 0xff000000 (238 MB) Lowmem : 0x80000000 – 0xc0000000 (1GB) abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem. abiv2 CPUs are all PIPT cache and they could support highmem. Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup memory page table for it. Link:https://lore.kernel.org/lkml/20180518215548.GH17671@n2100.armlinux.org.uk/ Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Christoph Hellwig <hch@infradead.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
75 lines
1.2 KiB
C
75 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_CKMMUV1_H
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#define __ASM_CSKY_CKMMUV1_H
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#include <abi/reg_ops.h>
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static inline int read_mmu_index(void)
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{
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return cprcr("cpcr0");
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}
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static inline void write_mmu_index(int value)
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{
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cpwcr("cpcr0", value);
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}
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static inline int read_mmu_entrylo0(void)
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{
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return cprcr("cpcr2") << 6;
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}
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static inline int read_mmu_entrylo1(void)
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{
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return cprcr("cpcr3") << 6;
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}
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static inline void write_mmu_pagemask(int value)
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{
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cpwcr("cpcr6", value);
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}
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static inline int read_mmu_entryhi(void)
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{
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return cprcr("cpcr4");
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}
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static inline void write_mmu_entryhi(int value)
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{
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cpwcr("cpcr4", value);
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}
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/*
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* TLB operations.
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*/
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static inline void tlb_probe(void)
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{
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cpwcr("cpcr8", 0x80000000);
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}
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static inline void tlb_read(void)
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{
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cpwcr("cpcr8", 0x40000000);
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}
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static inline void tlb_invalid_all(void)
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{
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cpwcr("cpcr8", 0x04000000);
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}
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static inline void tlb_invalid_indexed(void)
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{
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cpwcr("cpcr8", 0x02000000);
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}
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static inline void setup_pgd(unsigned long pgd, bool kernel)
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{
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cpwcr("cpcr29", pgd);
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}
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static inline unsigned long get_pgd(void)
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{
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return cprcr("cpcr29");
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}
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#endif /* __ASM_CSKY_CKMMUV1_H */
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