Russ Weight 0d70af3c25 fpga: bridge: Use standard dev_release for class driver ... The FPGA bridge class driver data structure is being treated as a managed resource instead of using the standard dev_release call-back function to release the class data structure. This change removes the managed resource code and combines the create() and register() functions into a single register() function. Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>		2021-11-28 14:02:13 -08:00
..
altera-cvp.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
altera-fpga2sdram.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
altera-freeze-bridge.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
altera-hps2fpga.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
altera-pr-ip-core-plat.c	fpga: fpga-mgr: altera-pr-ip: Simplify registration	2020-12-01 18:49:32 +01:00
altera-pr-ip-core.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
altera-ps-spi.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
dfl-afu-dma-region.c	fpga: dfl: afu: convert get_user_pages() --> pin_user_pages()	2020-06-18 18:12:06 -07:00
dfl-afu-error.c	fpga: dfl: afu: harden port enable logic	2021-03-24 11:15:04 -07:00
dfl-afu-main.c	fpga: dfl: afu: harden port enable logic	2021-03-24 11:15:04 -07:00
dfl-afu-region.c	fpga: dfl: afu: add afu sub feature support	2018-07-15 13:55:47 +02:00
dfl-afu.h	fpga: dfl: afu: harden port enable logic	2021-03-24 11:15:04 -07:00
dfl-fme-br.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
dfl-fme-error.c	fpga: dfl: fme: add interrupt support for global error reporting	2020-07-06 21:35:42 -07:00
dfl-fme-main.c	fpga: dfl: fme: add interrupt support for global error reporting	2020-07-06 21:35:42 -07:00
dfl-fme-mgr.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
dfl-fme-perf.c	fpga: dfl: fme: Fix cpu hotplug issue in performance reporting	2021-07-27 11:05:16 -07:00
dfl-fme-pr.c	fpga: fix spelling mistakes	2021-07-21 19:54:21 -07:00
dfl-fme-pr.h	fpga: dfl: fme: add partial reconfiguration sub feature support	2018-07-15 13:55:46 +02:00
dfl-fme-region.c	fpga: dfl-fme-region: Use platform_get_drvdata()	2018-11-26 20:47:10 +01:00
dfl-fme.h	fpga: dfl: fme: add performance reporting support	2020-04-28 15:49:28 +02:00
dfl-n3000-nios.c	fpga: fix spelling mistakes	2021-07-21 19:54:21 -07:00
dfl-pci.c	fpga: dfl: pci: add device IDs for Silicom N501x PAC cards	2021-07-24 15:10:30 -07:00
dfl.c	fpga: dfl: Avoid reads to AFU CSRs during enumeration	2021-09-16 15:20:55 -07:00
dfl.h	fpga: dfl: expose feature revision from struct dfl_device	2021-07-29 12:54:10 -07:00
fpga-bridge.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
fpga-mgr.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
fpga-region.c	fpga: region: Rename dev to parent for parent device	2021-06-15 09:29:55 +02:00
ice40-spi.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
Kconfig	FPGA Manager changes for 5.15-rc1	2021-08-05 14:26:03 +02:00
machxo2-spi.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
Makefile	fpga: versal-fpga: Add versal fpga manager driver	2021-07-21 13:14:09 +02:00
of-fpga-region.c	fpga: of-fpga-region: change FPGA indirect article to an	2021-06-09 14:51:25 +02:00
socfpga-a10.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
socfpga.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
stratix10-soc.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
ts73xx-fpga.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
versal-fpga.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
xilinx-pr-decoupler.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
xilinx-spi.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
zynq-fpga.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
zynqmp-fpga.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00