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![Vaibhav Jain](/assets/img/avatar_default.png)
Add a check at the beginning of cxl_probe function to ignore virtual pci devices created for each afu registered. This fixes the the errors messages logged about missing CXL vsec, when cxl probe is unable to find necessary vsec entries in device pci config space. The error message logged are of the form : cxl-pci 0004:00:00.0: ABORTING: CXL VSEC not found! cxl-pci 0004:00:00.0: cxl_init_adapter failed: -19 Cc: Ian Munsie <imunsie@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: fbarrat@linux.vnet.ibm.com Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
298 lines
6.4 KiB
C
298 lines
6.4 KiB
C
/*
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* Copyright 2014 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/pci.h>
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#include <misc/cxl.h>
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#include "cxl.h"
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static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
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{
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if (dma_mask < DMA_BIT_MASK(64)) {
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pr_info("%s only 64bit DMA supported on CXL", __func__);
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return -EIO;
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}
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*(pdev->dev.dma_mask) = dma_mask;
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return 0;
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}
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static int cxl_pci_probe_mode(struct pci_bus *bus)
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{
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return PCI_PROBE_NORMAL;
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}
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static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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return -ENODEV;
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}
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static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
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{
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/*
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* MSI should never be set but need still need to provide this call
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* back.
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*/
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}
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static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
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{
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struct pci_controller *phb;
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struct cxl_afu *afu;
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struct cxl_context *ctx;
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phb = pci_bus_to_host(dev->bus);
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afu = (struct cxl_afu *)phb->private_data;
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if (!cxl_ops->link_ok(afu->adapter, afu)) {
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dev_warn(&dev->dev, "%s: Device link is down, refusing to enable AFU\n", __func__);
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return false;
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}
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set_dma_ops(&dev->dev, &dma_direct_ops);
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set_dma_offset(&dev->dev, PAGE_OFFSET);
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/*
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* Allocate a context to do cxl things too. If we eventually do real
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* DMA ops, we'll need a default context to attach them to
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*/
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ctx = cxl_dev_context_init(dev);
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if (!ctx)
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return false;
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dev->dev.archdata.cxl_ctx = ctx;
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return (cxl_ops->afu_check_and_enable(afu) == 0);
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}
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static void cxl_pci_disable_device(struct pci_dev *dev)
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{
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struct cxl_context *ctx = cxl_get_context(dev);
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if (ctx) {
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if (ctx->status == STARTED) {
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dev_err(&dev->dev, "Default context started\n");
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return;
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}
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dev->dev.archdata.cxl_ctx = NULL;
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cxl_release_context(ctx);
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}
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}
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static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
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unsigned long type)
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{
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return 1;
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}
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static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
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{
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/* Should we do an AFU reset here ? */
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}
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static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
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{
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return (bus << 8) + devfn;
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}
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static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
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struct cxl_afu **_afu, int *_record)
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{
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struct pci_controller *phb;
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struct cxl_afu *afu;
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int record;
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phb = pci_bus_to_host(bus);
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if (phb == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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afu = (struct cxl_afu *)phb->private_data;
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record = cxl_pcie_cfg_record(bus->number, devfn);
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if (record > afu->crs_num)
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return PCIBIOS_DEVICE_NOT_FOUND;
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*_afu = afu;
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*_record = record;
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return 0;
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}
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static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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int rc, record;
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struct cxl_afu *afu;
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u8 val8;
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u16 val16;
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u32 val32;
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rc = cxl_pcie_config_info(bus, devfn, &afu, &record);
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if (rc)
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return rc;
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switch (len) {
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case 1:
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rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8);
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*val = val8;
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break;
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case 2:
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rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16);
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*val = val16;
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break;
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case 4:
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rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32);
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*val = val32;
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break;
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default:
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WARN_ON(1);
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}
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if (rc)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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int rc, record;
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struct cxl_afu *afu;
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rc = cxl_pcie_config_info(bus, devfn, &afu, &record);
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if (rc)
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return rc;
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switch (len) {
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case 1:
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rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff);
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break;
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case 2:
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rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff);
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break;
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case 4:
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rc = cxl_ops->afu_cr_write32(afu, record, offset, val);
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break;
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default:
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WARN_ON(1);
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}
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if (rc)
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return PCIBIOS_SET_FAILED;
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops cxl_pcie_pci_ops =
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{
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.read = cxl_pcie_read_config,
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.write = cxl_pcie_write_config,
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};
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static struct pci_controller_ops cxl_pci_controller_ops =
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{
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.probe_mode = cxl_pci_probe_mode,
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.enable_device_hook = cxl_pci_enable_device_hook,
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.disable_device = cxl_pci_disable_device,
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.release_device = cxl_pci_disable_device,
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.window_alignment = cxl_pci_window_alignment,
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.reset_secondary_bus = cxl_pci_reset_secondary_bus,
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.setup_msi_irqs = cxl_setup_msi_irqs,
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.teardown_msi_irqs = cxl_teardown_msi_irqs,
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.dma_set_mask = cxl_dma_set_mask,
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};
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int cxl_pci_vphb_add(struct cxl_afu *afu)
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{
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struct pci_dev *phys_dev;
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struct pci_controller *phb, *phys_phb;
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struct device_node *vphb_dn;
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struct device *parent;
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if (cpu_has_feature(CPU_FTR_HVMODE)) {
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phys_dev = to_pci_dev(afu->adapter->dev.parent);
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phys_phb = pci_bus_to_host(phys_dev->bus);
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vphb_dn = phys_phb->dn;
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parent = &phys_dev->dev;
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} else {
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vphb_dn = afu->adapter->dev.parent->of_node;
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parent = afu->adapter->dev.parent;
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}
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/* Alloc and setup PHB data structure */
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phb = pcibios_alloc_controller(vphb_dn);
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if (!phb)
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return -ENODEV;
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/* Setup parent in sysfs */
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phb->parent = parent;
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/* Setup the PHB using arch provided callback */
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phb->ops = &cxl_pcie_pci_ops;
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phb->cfg_addr = NULL;
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phb->cfg_data = 0;
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phb->private_data = afu;
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phb->controller_ops = cxl_pci_controller_ops;
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/* Scan the bus */
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pcibios_scan_phb(phb);
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if (phb->bus == NULL)
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return -ENXIO;
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/* Claim resources. This might need some rework as well depending
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* whether we are doing probe-only or not, like assigning unassigned
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* resources etc...
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*/
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pcibios_claim_one_bus(phb->bus);
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/* Add probed PCI devices to the device model */
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pci_bus_add_devices(phb->bus);
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afu->phb = phb;
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return 0;
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}
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void cxl_pci_vphb_remove(struct cxl_afu *afu)
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{
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struct pci_controller *phb;
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/* If there is no configuration record we won't have one of these */
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if (!afu || !afu->phb)
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return;
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phb = afu->phb;
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afu->phb = NULL;
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pci_remove_root_bus(phb->bus);
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pcibios_free_controller(phb);
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}
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bool cxl_pci_is_vphb_device(struct pci_dev *dev)
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{
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struct pci_controller *phb;
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phb = pci_bus_to_host(dev->bus);
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return (phb->ops == &cxl_pcie_pci_ops);
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}
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struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
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{
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struct pci_controller *phb;
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phb = pci_bus_to_host(dev->bus);
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return (struct cxl_afu *)phb->private_data;
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}
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EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
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unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
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{
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return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
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}
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EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);
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