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![Stephen Boyd](/assets/img/avatar_default.png)
The function selection bitfield is not always 3 bits wide. Sometimes it is 4 bits wide. Let's use the npins struct member to determine how many bits wide the function selection bitfield is so we clear the correct amount of bits in the register while remuxing the pins. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
933 lines
23 KiB
C
933 lines
23 KiB
C
/*
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* Copyright (c) 2013, Sony Mobile Communications AB.
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/slab.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/reboot.h>
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#include <linux/pm.h>
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#include <linux/log2.h>
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#include "../core.h"
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#include "../pinconf.h"
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#include "pinctrl-msm.h"
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#include "../pinctrl-utils.h"
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#define MAX_NR_GPIO 300
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#define PS_HOLD_OFFSET 0x820
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/**
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* struct msm_pinctrl - state for a pinctrl-msm device
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* @dev: device handle.
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* @pctrl: pinctrl handle.
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* @chip: gpiochip handle.
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* @restart_nb: restart notifier block.
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* @irq: parent irq for the TLMM irq_chip.
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* @lock: Spinlock to protect register resources as well
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* as msm_pinctrl data structures.
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* @enabled_irqs: Bitmap of currently enabled irqs.
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* @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
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* detection.
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* @soc; Reference to soc_data of platform specific data.
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* @regs: Base address for the TLMM register map.
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*/
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struct msm_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pctrl;
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struct gpio_chip chip;
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struct notifier_block restart_nb;
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int irq;
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spinlock_t lock;
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DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
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DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
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const struct msm_pinctrl_soc_data *soc;
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void __iomem *regs;
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};
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static int msm_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->ngroups;
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}
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static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
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unsigned group)
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{
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->groups[group].name;
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}
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static int msm_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned group,
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const unsigned **pins,
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unsigned *num_pins)
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{
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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*pins = pctrl->soc->groups[group].pins;
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*num_pins = pctrl->soc->groups[group].npins;
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return 0;
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}
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static const struct pinctrl_ops msm_pinctrl_ops = {
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.get_groups_count = msm_get_groups_count,
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.get_group_name = msm_get_group_name,
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.get_group_pins = msm_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
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.dt_free_map = pinctrl_utils_free_map,
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};
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static int msm_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->nfunctions;
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}
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static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
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unsigned function)
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{
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->functions[function].name;
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}
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static int msm_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned function,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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*groups = pctrl->soc->functions[function].groups;
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*num_groups = pctrl->soc->functions[function].ngroups;
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return 0;
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}
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static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned function,
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unsigned group)
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{
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct msm_pingroup *g;
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unsigned long flags;
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u32 val, mask;
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int i;
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g = &pctrl->soc->groups[group];
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mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
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for (i = 0; i < g->nfuncs; i++) {
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if (g->funcs[i] == function)
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break;
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}
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if (WARN_ON(i == g->nfuncs))
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return -EINVAL;
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spin_lock_irqsave(&pctrl->lock, flags);
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val = readl(pctrl->regs + g->ctl_reg);
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val &= mask;
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val |= i << g->mux_bit;
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writel(val, pctrl->regs + g->ctl_reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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static const struct pinmux_ops msm_pinmux_ops = {
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.get_functions_count = msm_get_functions_count,
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.get_function_name = msm_get_function_name,
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.get_function_groups = msm_get_function_groups,
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.set_mux = msm_pinmux_set_mux,
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};
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static int msm_config_reg(struct msm_pinctrl *pctrl,
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const struct msm_pingroup *g,
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unsigned param,
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unsigned *mask,
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unsigned *bit)
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{
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_BIAS_BUS_HOLD:
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case PIN_CONFIG_BIAS_PULL_UP:
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*bit = g->pull_bit;
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*mask = 3;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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*bit = g->drv_bit;
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*mask = 7;
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break;
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case PIN_CONFIG_OUTPUT:
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case PIN_CONFIG_INPUT_ENABLE:
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*bit = g->oe_bit;
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*mask = 1;
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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#define MSM_NO_PULL 0
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#define MSM_PULL_DOWN 1
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#define MSM_KEEPER 2
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#define MSM_PULL_UP 3
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static unsigned msm_regval_to_drive(u32 val)
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{
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return (val + 1) * 2;
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}
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static int msm_config_group_get(struct pinctrl_dev *pctldev,
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unsigned int group,
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unsigned long *config)
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{
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const struct msm_pingroup *g;
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned param = pinconf_to_config_param(*config);
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unsigned mask;
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unsigned arg;
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unsigned bit;
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int ret;
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u32 val;
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g = &pctrl->soc->groups[group];
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ret = msm_config_reg(pctrl, g, param, &mask, &bit);
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if (ret < 0)
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return ret;
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val = readl(pctrl->regs + g->ctl_reg);
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arg = (val >> bit) & mask;
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/* Convert register value to pinconf value */
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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arg = arg == MSM_NO_PULL;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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arg = arg == MSM_PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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arg = arg == MSM_KEEPER;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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arg = arg == MSM_PULL_UP;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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arg = msm_regval_to_drive(arg);
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break;
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case PIN_CONFIG_OUTPUT:
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/* Pin is not output */
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if (!arg)
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return -EINVAL;
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val = readl(pctrl->regs + g->io_reg);
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arg = !!(val & BIT(g->in_bit));
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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/* Pin is output */
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if (arg)
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return -EINVAL;
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arg = 1;
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break;
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default:
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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static int msm_config_group_set(struct pinctrl_dev *pctldev,
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unsigned group,
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unsigned long *configs,
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unsigned num_configs)
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{
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const struct msm_pingroup *g;
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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unsigned param;
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unsigned mask;
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unsigned arg;
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unsigned bit;
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int ret;
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u32 val;
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int i;
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g = &pctrl->soc->groups[group];
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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ret = msm_config_reg(pctrl, g, param, &mask, &bit);
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if (ret < 0)
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return ret;
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/* Convert pinconf values to register values */
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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arg = MSM_NO_PULL;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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arg = MSM_PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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arg = MSM_KEEPER;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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arg = MSM_PULL_UP;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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/* Check for invalid values */
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if (arg > 16 || arg < 2 || (arg % 2) != 0)
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arg = -1;
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else
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arg = (arg / 2) - 1;
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break;
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case PIN_CONFIG_OUTPUT:
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/* set output value */
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spin_lock_irqsave(&pctrl->lock, flags);
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val = readl(pctrl->regs + g->io_reg);
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if (arg)
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val |= BIT(g->out_bit);
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else
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val &= ~BIT(g->out_bit);
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writel(val, pctrl->regs + g->io_reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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/* enable output */
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arg = 1;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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/* disable output */
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arg = 0;
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break;
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default:
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dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
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param);
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return -EINVAL;
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}
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/* Range-check user-supplied value */
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if (arg & ~mask) {
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dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
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return -EINVAL;
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}
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spin_lock_irqsave(&pctrl->lock, flags);
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val = readl(pctrl->regs + g->ctl_reg);
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val &= ~(mask << bit);
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val |= arg << bit;
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writel(val, pctrl->regs + g->ctl_reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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return 0;
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}
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static const struct pinconf_ops msm_pinconf_ops = {
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.is_generic = true,
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.pin_config_group_get = msm_config_group_get,
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.pin_config_group_set = msm_config_group_set,
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};
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static struct pinctrl_desc msm_pinctrl_desc = {
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.pctlops = &msm_pinctrl_ops,
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.pmxops = &msm_pinmux_ops,
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.confops = &msm_pinconf_ops,
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.owner = THIS_MODULE,
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};
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static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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const struct msm_pingroup *g;
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struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
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unsigned long flags;
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u32 val;
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g = &pctrl->soc->groups[offset];
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spin_lock_irqsave(&pctrl->lock, flags);
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val = readl(pctrl->regs + g->ctl_reg);
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val &= ~BIT(g->oe_bit);
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writel(val, pctrl->regs + g->ctl_reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
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{
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const struct msm_pingroup *g;
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struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
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unsigned long flags;
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u32 val;
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g = &pctrl->soc->groups[offset];
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spin_lock_irqsave(&pctrl->lock, flags);
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val = readl(pctrl->regs + g->io_reg);
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if (value)
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val |= BIT(g->out_bit);
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else
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val &= ~BIT(g->out_bit);
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writel(val, pctrl->regs + g->io_reg);
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val = readl(pctrl->regs + g->ctl_reg);
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val |= BIT(g->oe_bit);
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writel(val, pctrl->regs + g->ctl_reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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const struct msm_pingroup *g;
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struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
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u32 val;
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g = &pctrl->soc->groups[offset];
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val = readl(pctrl->regs + g->io_reg);
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return !!(val & BIT(g->in_bit));
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}
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static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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const struct msm_pingroup *g;
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struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
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unsigned long flags;
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u32 val;
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g = &pctrl->soc->groups[offset];
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spin_lock_irqsave(&pctrl->lock, flags);
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val = readl(pctrl->regs + g->io_reg);
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if (value)
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val |= BIT(g->out_bit);
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else
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val &= ~BIT(g->out_bit);
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writel(val, pctrl->regs + g->io_reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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#ifdef CONFIG_DEBUG_FS
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#include <linux/seq_file.h>
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static void msm_gpio_dbg_show_one(struct seq_file *s,
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struct pinctrl_dev *pctldev,
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struct gpio_chip *chip,
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unsigned offset,
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unsigned gpio)
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{
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const struct msm_pingroup *g;
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struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
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unsigned func;
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int is_out;
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int drive;
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int pull;
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u32 ctl_reg;
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static const char * const pulls[] = {
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"no pull",
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"pull down",
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"keeper",
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"pull up"
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};
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g = &pctrl->soc->groups[offset];
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ctl_reg = readl(pctrl->regs + g->ctl_reg);
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is_out = !!(ctl_reg & BIT(g->oe_bit));
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func = (ctl_reg >> g->mux_bit) & 7;
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drive = (ctl_reg >> g->drv_bit) & 7;
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pull = (ctl_reg >> g->pull_bit) & 3;
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seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
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seq_printf(s, " %dmA", msm_regval_to_drive(drive));
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seq_printf(s, " %s", pulls[pull]);
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}
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static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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{
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unsigned gpio = chip->base;
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unsigned i;
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for (i = 0; i < chip->ngpio; i++, gpio++) {
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msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
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seq_puts(s, "\n");
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}
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}
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#else
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#define msm_gpio_dbg_show NULL
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#endif
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static struct gpio_chip msm_gpio_template = {
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.direction_input = msm_gpio_direction_input,
|
|
.direction_output = msm_gpio_direction_output,
|
|
.get = msm_gpio_get,
|
|
.set = msm_gpio_set,
|
|
.request = gpiochip_generic_request,
|
|
.free = gpiochip_generic_free,
|
|
.dbg_show = msm_gpio_dbg_show,
|
|
};
|
|
|
|
/* For dual-edge interrupts in software, since some hardware has no
|
|
* such support:
|
|
*
|
|
* At appropriate moments, this function may be called to flip the polarity
|
|
* settings of both-edge irq lines to try and catch the next edge.
|
|
*
|
|
* The attempt is considered successful if:
|
|
* - the status bit goes high, indicating that an edge was caught, or
|
|
* - the input value of the gpio doesn't change during the attempt.
|
|
* If the value changes twice during the process, that would cause the first
|
|
* test to fail but would force the second, as two opposite
|
|
* transitions would cause a detection no matter the polarity setting.
|
|
*
|
|
* The do-loop tries to sledge-hammer closed the timing hole between
|
|
* the initial value-read and the polarity-write - if the line value changes
|
|
* during that window, an interrupt is lost, the new polarity setting is
|
|
* incorrect, and the first success test will fail, causing a retry.
|
|
*
|
|
* Algorithm comes from Google's msmgpio driver.
|
|
*/
|
|
static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
|
|
const struct msm_pingroup *g,
|
|
struct irq_data *d)
|
|
{
|
|
int loop_limit = 100;
|
|
unsigned val, val2, intstat;
|
|
unsigned pol;
|
|
|
|
do {
|
|
val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
|
|
|
|
pol = readl(pctrl->regs + g->intr_cfg_reg);
|
|
pol ^= BIT(g->intr_polarity_bit);
|
|
writel(pol, pctrl->regs + g->intr_cfg_reg);
|
|
|
|
val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
|
|
intstat = readl(pctrl->regs + g->intr_status_reg);
|
|
if (intstat || (val == val2))
|
|
return;
|
|
} while (loop_limit-- > 0);
|
|
dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
|
|
val, val2);
|
|
}
|
|
|
|
static void msm_gpio_irq_mask(struct irq_data *d)
|
|
{
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
|
|
const struct msm_pingroup *g;
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
g = &pctrl->soc->groups[d->hwirq];
|
|
|
|
spin_lock_irqsave(&pctrl->lock, flags);
|
|
|
|
val = readl(pctrl->regs + g->intr_cfg_reg);
|
|
val &= ~BIT(g->intr_enable_bit);
|
|
writel(val, pctrl->regs + g->intr_cfg_reg);
|
|
|
|
clear_bit(d->hwirq, pctrl->enabled_irqs);
|
|
|
|
spin_unlock_irqrestore(&pctrl->lock, flags);
|
|
}
|
|
|
|
static void msm_gpio_irq_unmask(struct irq_data *d)
|
|
{
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
|
|
const struct msm_pingroup *g;
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
g = &pctrl->soc->groups[d->hwirq];
|
|
|
|
spin_lock_irqsave(&pctrl->lock, flags);
|
|
|
|
val = readl(pctrl->regs + g->intr_status_reg);
|
|
val &= ~BIT(g->intr_status_bit);
|
|
writel(val, pctrl->regs + g->intr_status_reg);
|
|
|
|
val = readl(pctrl->regs + g->intr_cfg_reg);
|
|
val |= BIT(g->intr_enable_bit);
|
|
writel(val, pctrl->regs + g->intr_cfg_reg);
|
|
|
|
set_bit(d->hwirq, pctrl->enabled_irqs);
|
|
|
|
spin_unlock_irqrestore(&pctrl->lock, flags);
|
|
}
|
|
|
|
static void msm_gpio_irq_ack(struct irq_data *d)
|
|
{
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
|
|
const struct msm_pingroup *g;
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
g = &pctrl->soc->groups[d->hwirq];
|
|
|
|
spin_lock_irqsave(&pctrl->lock, flags);
|
|
|
|
val = readl(pctrl->regs + g->intr_status_reg);
|
|
if (g->intr_ack_high)
|
|
val |= BIT(g->intr_status_bit);
|
|
else
|
|
val &= ~BIT(g->intr_status_bit);
|
|
writel(val, pctrl->regs + g->intr_status_reg);
|
|
|
|
if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
|
|
msm_gpio_update_dual_edge_pos(pctrl, g, d);
|
|
|
|
spin_unlock_irqrestore(&pctrl->lock, flags);
|
|
}
|
|
|
|
static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
|
{
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
|
|
const struct msm_pingroup *g;
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
g = &pctrl->soc->groups[d->hwirq];
|
|
|
|
spin_lock_irqsave(&pctrl->lock, flags);
|
|
|
|
/*
|
|
* For hw without possibility of detecting both edges
|
|
*/
|
|
if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
|
|
set_bit(d->hwirq, pctrl->dual_edge_irqs);
|
|
else
|
|
clear_bit(d->hwirq, pctrl->dual_edge_irqs);
|
|
|
|
/* Route interrupts to application cpu */
|
|
val = readl(pctrl->regs + g->intr_target_reg);
|
|
val &= ~(7 << g->intr_target_bit);
|
|
val |= g->intr_target_kpss_val << g->intr_target_bit;
|
|
writel(val, pctrl->regs + g->intr_target_reg);
|
|
|
|
/* Update configuration for gpio.
|
|
* RAW_STATUS_EN is left on for all gpio irqs. Due to the
|
|
* internal circuitry of TLMM, toggling the RAW_STATUS
|
|
* could cause the INTR_STATUS to be set for EDGE interrupts.
|
|
*/
|
|
val = readl(pctrl->regs + g->intr_cfg_reg);
|
|
val |= BIT(g->intr_raw_status_bit);
|
|
if (g->intr_detection_width == 2) {
|
|
val &= ~(3 << g->intr_detection_bit);
|
|
val &= ~(1 << g->intr_polarity_bit);
|
|
switch (type) {
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
val |= 1 << g->intr_detection_bit;
|
|
val |= BIT(g->intr_polarity_bit);
|
|
break;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
val |= 2 << g->intr_detection_bit;
|
|
val |= BIT(g->intr_polarity_bit);
|
|
break;
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
val |= 3 << g->intr_detection_bit;
|
|
val |= BIT(g->intr_polarity_bit);
|
|
break;
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
break;
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
val |= BIT(g->intr_polarity_bit);
|
|
break;
|
|
}
|
|
} else if (g->intr_detection_width == 1) {
|
|
val &= ~(1 << g->intr_detection_bit);
|
|
val &= ~(1 << g->intr_polarity_bit);
|
|
switch (type) {
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
val |= BIT(g->intr_detection_bit);
|
|
val |= BIT(g->intr_polarity_bit);
|
|
break;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
val |= BIT(g->intr_detection_bit);
|
|
break;
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
val |= BIT(g->intr_detection_bit);
|
|
val |= BIT(g->intr_polarity_bit);
|
|
break;
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
break;
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
val |= BIT(g->intr_polarity_bit);
|
|
break;
|
|
}
|
|
} else {
|
|
BUG();
|
|
}
|
|
writel(val, pctrl->regs + g->intr_cfg_reg);
|
|
|
|
if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
|
|
msm_gpio_update_dual_edge_pos(pctrl, g, d);
|
|
|
|
spin_unlock_irqrestore(&pctrl->lock, flags);
|
|
|
|
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
|
|
irq_set_handler_locked(d, handle_level_irq);
|
|
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
|
irq_set_handler_locked(d, handle_edge_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
|
|
{
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&pctrl->lock, flags);
|
|
|
|
irq_set_irq_wake(pctrl->irq, on);
|
|
|
|
spin_unlock_irqrestore(&pctrl->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct irq_chip msm_gpio_irq_chip = {
|
|
.name = "msmgpio",
|
|
.irq_mask = msm_gpio_irq_mask,
|
|
.irq_unmask = msm_gpio_irq_unmask,
|
|
.irq_ack = msm_gpio_irq_ack,
|
|
.irq_set_type = msm_gpio_irq_set_type,
|
|
.irq_set_wake = msm_gpio_irq_set_wake,
|
|
};
|
|
|
|
static void msm_gpio_irq_handler(struct irq_desc *desc)
|
|
{
|
|
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
|
const struct msm_pingroup *g;
|
|
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
int irq_pin;
|
|
int handled = 0;
|
|
u32 val;
|
|
int i;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
/*
|
|
* Each pin has it's own IRQ status register, so use
|
|
* enabled_irq bitmap to limit the number of reads.
|
|
*/
|
|
for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
|
|
g = &pctrl->soc->groups[i];
|
|
val = readl(pctrl->regs + g->intr_status_reg);
|
|
if (val & BIT(g->intr_status_bit)) {
|
|
irq_pin = irq_find_mapping(gc->irqdomain, i);
|
|
generic_handle_irq(irq_pin);
|
|
handled++;
|
|
}
|
|
}
|
|
|
|
/* No interrupts were flagged */
|
|
if (handled == 0)
|
|
handle_bad_irq(desc);
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static int msm_gpio_init(struct msm_pinctrl *pctrl)
|
|
{
|
|
struct gpio_chip *chip;
|
|
int ret;
|
|
unsigned ngpio = pctrl->soc->ngpios;
|
|
|
|
if (WARN_ON(ngpio > MAX_NR_GPIO))
|
|
return -EINVAL;
|
|
|
|
chip = &pctrl->chip;
|
|
chip->base = 0;
|
|
chip->ngpio = ngpio;
|
|
chip->label = dev_name(pctrl->dev);
|
|
chip->parent = pctrl->dev;
|
|
chip->owner = THIS_MODULE;
|
|
chip->of_node = pctrl->dev->of_node;
|
|
|
|
ret = gpiochip_add_data(&pctrl->chip, pctrl);
|
|
if (ret) {
|
|
dev_err(pctrl->dev, "Failed register gpiochip\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
|
|
if (ret) {
|
|
dev_err(pctrl->dev, "Failed to add pin range\n");
|
|
gpiochip_remove(&pctrl->chip);
|
|
return ret;
|
|
}
|
|
|
|
ret = gpiochip_irqchip_add(chip,
|
|
&msm_gpio_irq_chip,
|
|
0,
|
|
handle_edge_irq,
|
|
IRQ_TYPE_NONE);
|
|
if (ret) {
|
|
dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
|
|
gpiochip_remove(&pctrl->chip);
|
|
return -ENOSYS;
|
|
}
|
|
|
|
gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
|
|
msm_gpio_irq_handler);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
|
|
void *data)
|
|
{
|
|
struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
|
|
|
|
writel(0, pctrl->regs + PS_HOLD_OFFSET);
|
|
mdelay(1000);
|
|
return NOTIFY_DONE;
|
|
}
|
|
|
|
static struct msm_pinctrl *poweroff_pctrl;
|
|
|
|
static void msm_ps_hold_poweroff(void)
|
|
{
|
|
msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
|
|
}
|
|
|
|
static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
|
|
{
|
|
int i;
|
|
const struct msm_function *func = pctrl->soc->functions;
|
|
|
|
for (i = 0; i < pctrl->soc->nfunctions; i++)
|
|
if (!strcmp(func[i].name, "ps_hold")) {
|
|
pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
|
|
pctrl->restart_nb.priority = 128;
|
|
if (register_restart_handler(&pctrl->restart_nb))
|
|
dev_err(pctrl->dev,
|
|
"failed to setup restart handler.\n");
|
|
poweroff_pctrl = pctrl;
|
|
pm_power_off = msm_ps_hold_poweroff;
|
|
break;
|
|
}
|
|
}
|
|
|
|
int msm_pinctrl_probe(struct platform_device *pdev,
|
|
const struct msm_pinctrl_soc_data *soc_data)
|
|
{
|
|
struct msm_pinctrl *pctrl;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
|
|
if (!pctrl) {
|
|
dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
|
|
return -ENOMEM;
|
|
}
|
|
pctrl->dev = &pdev->dev;
|
|
pctrl->soc = soc_data;
|
|
pctrl->chip = msm_gpio_template;
|
|
|
|
spin_lock_init(&pctrl->lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(pctrl->regs))
|
|
return PTR_ERR(pctrl->regs);
|
|
|
|
msm_pinctrl_setup_pm_reset(pctrl);
|
|
|
|
pctrl->irq = platform_get_irq(pdev, 0);
|
|
if (pctrl->irq < 0) {
|
|
dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
|
|
return pctrl->irq;
|
|
}
|
|
|
|
msm_pinctrl_desc.name = dev_name(&pdev->dev);
|
|
msm_pinctrl_desc.pins = pctrl->soc->pins;
|
|
msm_pinctrl_desc.npins = pctrl->soc->npins;
|
|
pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
|
|
pctrl);
|
|
if (IS_ERR(pctrl->pctrl)) {
|
|
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
|
|
return PTR_ERR(pctrl->pctrl);
|
|
}
|
|
|
|
ret = msm_gpio_init(pctrl);
|
|
if (ret)
|
|
return ret;
|
|
|
|
platform_set_drvdata(pdev, pctrl);
|
|
|
|
dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(msm_pinctrl_probe);
|
|
|
|
int msm_pinctrl_remove(struct platform_device *pdev)
|
|
{
|
|
struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
|
|
|
|
gpiochip_remove(&pctrl->chip);
|
|
|
|
unregister_restart_handler(&pctrl->restart_nb);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(msm_pinctrl_remove);
|
|
|