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The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a pre-divider. Update socfpga.dtsi to represent those dividers for these clocks. Re-use the "div-reg" property that was used for the socfpga-gate-clock as this is the same thing. Also update the documentation. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
30 lines
1.4 KiB
Text
30 lines
1.4 KiB
Text
Device Tree Clock bindings for Altera's SoCFPGA platform
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"altr,socfpga-pll-clock" - for a PLL clock
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"altr,socfpga-perip-clock" - The peripheral clock divided from the
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PLL clock.
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"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
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can get gated.
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- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
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- clocks : shall be the input parent clock phandle for the clock. This is
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either an oscillator or a pll output.
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- #clock-cells : from common clock binding, shall be set to 0.
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Optional properties:
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- fixed-divider : If clocks have a fixed divider value, use this property.
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- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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and the bit index.
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- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
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the divider register, bit shift, and width.
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- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
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the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
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value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
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hold/delay times that is needed for the SD/MMC CIU clock. The values of both
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can be 0-315 degrees, in 45 degree increments.
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