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2cabc45237
Add information for Cortex A7 PLL clock in Qualcomm platform SDX65. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com
51 lines
1,000 B
YAML
51 lines
1,000 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm A7 PLL Binding
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description:
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The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
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frequency clock to the CPU.
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properties:
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compatible:
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enum:
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- qcom,sdx55-a7pll
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reg:
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maxItems: 1
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'#clock-cells':
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const: 0
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clocks:
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items:
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- description: board XO clock
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clock-names:
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items:
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- const: bi_tcxo
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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a7pll: clock@17808000 {
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compatible = "qcom,sdx55-a7pll";
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reg = <0x17808000 0x1000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "bi_tcxo";
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#clock-cells = <0>;
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};
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