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The QEMU virt and spike machines currently export a riscv,isa string of "rv64imafdcsuh", While the RISC-V foundation has been ratifying a bunch of extenstions etc, the kernel has remained relatively static with what hardware is supported - but the same is not true of QEMU. Using the virt machine and running dt-validate on the dumped dtb fails, partly due to the unexpected isa string. Rather than enumerate the many many possbilities, change the pattern to a regex, with the following assumptions: - ima are required - the single letter order is fixed & we don't care about things that can't even do "ima" - the standard multi letter extensions are all in a "_z<foo>" format where the first letter of <foo> is a valid single letter extension - _s & _h are used for supervisor and hyper visor extensions - convention says that after the first two chars, a standard multi letter extension name could be an english word (ifencei anyone?) so it's not worth restricting the charset - as the above is just convention, don't apply any charset restrictions to reduce future churn - vendor ISA extensions begind with _x and have no charset restrictions - we don't care about an e extension from an OS pov - that attempting to validate the contents of the multiletter extensions with dt-validate beyond the formatting is a futile, massively verbose or unwieldy exercise at best The following limitations also apply: - multi letter extension ordering is not enforced. dt-schema does not appear to allow for named match groups, so the resulting regex would be even more of a headache - ditto for the numbered extensions Finally, add me as a maintainer of the binding so that when it breaks in the future, I can be held responsible! Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Guo Ren <guoren@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220823183319.3314940-4-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
186 lines
5.5 KiB
YAML
186 lines
5.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR MIT)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/cpus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V bindings for 'cpus' DT nodes
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maintainers:
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- Paul Walmsley <paul.walmsley@sifive.com>
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- Palmer Dabbelt <palmer@sifive.com>
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- Conor Dooley <conor@kernel.org>
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description: |
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This document uses some terminology common to the RISC-V community
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that is not widely used, the definitions of which are listed here:
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hart: A hardware execution context, which contains all the state
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mandated by the RISC-V ISA: a PC and some registers. This
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terminology is designed to disambiguate software's view of execution
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contexts from any particular microarchitectural implementation
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strategy. For example, an Intel laptop containing one socket with
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two cores, each of which has two hyperthreads, could be described as
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having four harts.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- sifive,rocket0
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- sifive,bullet0
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- sifive,e5
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- sifive,e7
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- sifive,e71
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- sifive,u74-mc
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- sifive,u54
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- sifive,u74
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- sifive,u5
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- sifive,u7
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- canaan,k210
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- const: riscv
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- items:
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- enum:
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- sifive,e51
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- sifive,u54-mc
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- const: sifive,rocket0
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- const: riscv
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- const: riscv # Simulator only
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description:
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Identifies that the hart uses the RISC-V instruction set
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and identifies the type of the hart.
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mmu-type:
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description:
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Identifies the MMU address translation mode used on this
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hart. These values originate from the RISC-V Privileged
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Specification document, available from
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https://riscv.org/specifications/
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$ref: "/schemas/types.yaml#/definitions/string"
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enum:
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- riscv,sv32
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- riscv,sv39
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- riscv,sv48
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- riscv,none
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riscv,cbom-block-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The blocksize in bytes for the Zicbom cache operations.
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riscv,isa:
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description:
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Identifies the specific RISC-V instruction set architecture
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supported by the hart. These are documented in the RISC-V
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User-Level ISA document, available from
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https://riscv.org/specifications/
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While the isa strings in ISA specification are case
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insensitive, letters in the riscv,isa string must be all
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lowercase to simplify parsing.
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$ref: "/schemas/types.yaml#/definitions/string"
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pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
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# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
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timebase-frequency: false
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interrupt-controller:
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type: object
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description: Describes the CPU's local interrupt controller
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properties:
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'#interrupt-cells':
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const: 1
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compatible:
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const: riscv,cpu-intc
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interrupt-controller: true
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required:
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- '#interrupt-cells'
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- compatible
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- interrupt-controller
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cpu-idle-states:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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items:
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maxItems: 1
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description: |
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List of phandles to idle state nodes supported
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by this hart (see ./idle-states.yaml).
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required:
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- riscv,isa
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- interrupt-controller
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additionalProperties: true
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examples:
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- |
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// Example 1: SiFive Freedom U540G Development Kit
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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cpu_intc0: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@1 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu_intc1: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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- |
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// Example 2: Spike ISA Simulator with 1 Hart
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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...
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