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![Ingo Molnar](/assets/img/avatar_default.png)
This patch (written by me and also containing many suggestions of Arjan van de Ven) does a major cleanup of the spinlock code. It does the following things: - consolidates and enhances the spinlock/rwlock debugging code - simplifies the asm/spinlock.h files - encapsulates the raw spinlock type and moves generic spinlock features (such as ->break_lock) into the generic code. - cleans up the spinlock code hierarchy to get rid of the spaghetti. Most notably there's now only a single variant of the debugging code, located in lib/spinlock_debug.c. (previously we had one SMP debugging variant per architecture, plus a separate generic one for UP builds) Also, i've enhanced the rwlock debugging facility, it will now track write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too. All locks have lockup detection now, which will work for both soft and hard spin/rwlock lockups. The arch-level include files now only contain the minimally necessary subset of the spinlock code - all the rest that can be generalized now lives in the generic headers: include/asm-i386/spinlock_types.h | 16 include/asm-x86_64/spinlock_types.h | 16 I have also split up the various spinlock variants into separate files, making it easier to see which does what. The new layout is: SMP | UP ----------------------------|----------------------------------- asm/spinlock_types_smp.h | linux/spinlock_types_up.h linux/spinlock_types.h | linux/spinlock_types.h asm/spinlock_smp.h | linux/spinlock_up.h linux/spinlock_api_smp.h | linux/spinlock_api_up.h linux/spinlock.h | linux/spinlock.h /* * here's the role of the various spinlock/rwlock related include files: * * on SMP builds: * * asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the * initializers * * linux/spinlock_types.h: * defines the generic type and initializers * * asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel * implementations, mostly inline assembly code * * (also included on UP-debug builds:) * * linux/spinlock_api_smp.h: * contains the prototypes for the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. * * on UP builds: * * linux/spinlock_type_up.h: * contains the generic, simplified UP spinlock type. * (which is an empty structure on non-debug builds) * * linux/spinlock_types.h: * defines the generic type and initializers * * linux/spinlock_up.h: * contains the __raw_spin_*()/etc. version of UP * builds. (which are NOPs on non-debug, non-preempt * builds) * * (included on UP-non-debug builds:) * * linux/spinlock_api_up.h: * builds the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. */ All SMP and UP architectures are converted by this patch. arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should be mostly fine. From: Grant Grundler <grundler@parisc-linux.org> Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU). Builds 32-bit SMP kernel (not booted or tested). I did not try to build non-SMP kernels. That should be trivial to fix up later if necessary. I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids some ugly nesting of linux/*.h and asm/*.h files. Those particular locks are well tested and contained entirely inside arch specific code. I do NOT expect any new issues to arise with them. If someone does ever need to use debug/metrics with them, then they will need to unravel this hairball between spinlocks, atomic ops, and bit ops that exist only because parisc has exactly one atomic instruction: LDCW (load and clear word). From: "Luck, Tony" <tony.luck@intel.com> ia64 fix Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjanv@infradead.org> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Cc: Matthew Wilcox <willy@debian.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se> Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
225 lines
4.8 KiB
C
225 lines
4.8 KiB
C
/* spinlock.h: 64-bit Sparc spinlock support.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef __SPARC64_SPINLOCK_H
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#define __SPARC64_SPINLOCK_H
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#include <linux/config.h>
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#include <linux/threads.h> /* For NR_CPUS */
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#ifndef __ASSEMBLY__
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/* To get debugging spinlocks which detect and catch
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* deadlock situations, set CONFIG_DEBUG_SPINLOCK
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* and rebuild your kernel.
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*/
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/* All of these locking primitives are expected to work properly
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* even in an RMO memory model, which currently is what the kernel
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* runs in.
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*
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* There is another issue. Because we play games to save cycles
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* in the non-contention case, we need to be extra careful about
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* branch targets into the "spinning" code. They live in their
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* own section, but the newer V9 branches have a shorter range
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* than the traditional 32-bit sparc branch variants. The rule
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* is that the branches that go into and out of the spinner sections
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* must be pre-V9 branches.
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*/
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#define __raw_spin_is_locked(lp) ((lp)->lock != 0)
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#define __raw_spin_unlock_wait(lp) \
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do { rmb(); \
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} while((lp)->lock)
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldstub [%1], %0\n"
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" membar #StoreLoad | #StoreStore\n"
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" brnz,pn %0, 2f\n"
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" nop\n"
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" .subsection 2\n"
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"2: ldub [%1], %0\n"
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" membar #LoadLoad\n"
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" brnz,pt %0, 2b\n"
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" nop\n"
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" ba,a,pt %%xcc, 1b\n"
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" .previous"
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: "=&r" (tmp)
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: "r" (lock)
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: "memory");
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}
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned long result;
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__asm__ __volatile__(
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" ldstub [%1], %0\n"
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" membar #StoreLoad | #StoreStore"
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: "=r" (result)
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: "r" (lock)
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: "memory");
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return (result == 0UL);
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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" membar #StoreStore | #LoadStore\n"
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" stb %%g0, [%0]"
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: /* No outputs */
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: "r" (lock)
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: "memory");
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}
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static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__(
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"1: ldstub [%2], %0\n"
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" membar #StoreLoad | #StoreStore\n"
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" brnz,pn %0, 2f\n"
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" nop\n"
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" .subsection 2\n"
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"2: rdpr %%pil, %1\n"
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" wrpr %3, %%pil\n"
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"3: ldub [%2], %0\n"
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" membar #LoadLoad\n"
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" brnz,pt %0, 3b\n"
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" nop\n"
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" ba,pt %%xcc, 1b\n"
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" wrpr %1, %%pil\n"
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" .previous"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r"(lock), "r"(flags)
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: "memory");
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}
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/* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
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static void inline __read_lock(raw_rwlock_t *lock)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__ (
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"1: ldsw [%2], %0\n"
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" brlz,pn %0, 2f\n"
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"4: add %0, 1, %1\n"
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" cas [%2], %0, %1\n"
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" cmp %0, %1\n"
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" membar #StoreLoad | #StoreStore\n"
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" bne,pn %%icc, 1b\n"
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" nop\n"
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" .subsection 2\n"
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"2: ldsw [%2], %0\n"
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" membar #LoadLoad\n"
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" brlz,pt %0, 2b\n"
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" nop\n"
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" ba,a,pt %%xcc, 4b\n"
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" .previous"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (lock)
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: "memory");
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}
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static void inline __read_unlock(raw_rwlock_t *lock)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__(
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" membar #StoreLoad | #LoadLoad\n"
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"1: lduw [%2], %0\n"
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" sub %0, 1, %1\n"
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" cas [%2], %0, %1\n"
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" cmp %0, %1\n"
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" bne,pn %%xcc, 1b\n"
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" nop"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (lock)
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: "memory");
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}
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static void inline __write_lock(raw_rwlock_t *lock)
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{
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unsigned long mask, tmp1, tmp2;
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mask = 0x80000000UL;
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__asm__ __volatile__(
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"1: lduw [%2], %0\n"
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" brnz,pn %0, 2f\n"
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"4: or %0, %3, %1\n"
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" cas [%2], %0, %1\n"
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" cmp %0, %1\n"
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" membar #StoreLoad | #StoreStore\n"
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" bne,pn %%icc, 1b\n"
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" nop\n"
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" .subsection 2\n"
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"2: lduw [%2], %0\n"
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" membar #LoadLoad\n"
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" brnz,pt %0, 2b\n"
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" nop\n"
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" ba,a,pt %%xcc, 4b\n"
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" .previous"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (lock), "r" (mask)
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: "memory");
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}
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static void inline __write_unlock(raw_rwlock_t *lock)
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{
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__asm__ __volatile__(
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" membar #LoadStore | #StoreStore\n"
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" stw %%g0, [%0]"
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: /* no outputs */
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: "r" (lock)
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: "memory");
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}
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static int inline __write_trylock(raw_rwlock_t *lock)
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{
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unsigned long mask, tmp1, tmp2, result;
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mask = 0x80000000UL;
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__asm__ __volatile__(
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" mov 0, %2\n"
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"1: lduw [%3], %0\n"
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" brnz,pn %0, 2f\n"
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" or %0, %4, %1\n"
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" cas [%3], %0, %1\n"
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" cmp %0, %1\n"
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" membar #StoreLoad | #StoreStore\n"
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" bne,pn %%icc, 1b\n"
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" nop\n"
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" mov 1, %2\n"
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"2:"
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: "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)
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: "r" (lock), "r" (mask)
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: "memory");
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return result;
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}
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#define __raw_read_lock(p) __read_lock(p)
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#define __raw_read_unlock(p) __read_unlock(p)
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#define __raw_write_lock(p) __write_lock(p)
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#define __raw_write_unlock(p) __write_unlock(p)
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#define __raw_write_trylock(p) __write_trylock(p)
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#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
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#define __raw_read_can_lock(rw) (!((rw)->lock & 0x80000000UL))
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#define __raw_write_can_lock(rw) (!(rw)->lock)
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__SPARC64_SPINLOCK_H) */
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