Peter Rosin 02f513a097 pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories. ... The DDRSDR controller fails miserably to put LPDDR1 memories in self-refresh. Force the controller to think it has DDR2 memories during the self-refresh period, as the DDR2 self-refresh spec is equivalent to LPDDR1, and is correctly implemented in the controller. Assume that the second controller has the same fault, but that is untested. Signed-off-by: Peter Rosin <peda@axentia.se> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>		2015-03-03 19:43:59 +01:00
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at91	pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.	2015-03-03 19:43:59 +01:00
tegra	soc/tegra: Add Tegra132 support	2015-01-09 16:13:57 +01:00