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e021ae7f51
Add required ports of the Alternative scheme for Andes CPU cores. I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason cache management needs a software workaround. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1 Link: https://lore.kernel.org/r/20230818135723.80612-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
7 lines
171 B
Makefile
7 lines
171 B
Makefile
ifdef CONFIG_RELOCATABLE
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KBUILD_CFLAGS += -fno-pie
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endif
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obj-$(CONFIG_ERRATA_ANDES) += andes/
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obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
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obj-$(CONFIG_ERRATA_THEAD) += thead/
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