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e021ae7f51
Add required ports of the Alternative scheme for Andes CPU cores. I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason cache management needs a software workaround. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1 Link: https://lore.kernel.org/r/20230818135723.80612-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Erratas to be applied for Andes CPU cores
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*
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* Copyright (C) 2023 Renesas Electronics Corporation.
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*
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* Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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*/
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#include <linux/memory.h>
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#include <linux/module.h>
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#include <asm/alternative.h>
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#include <asm/cacheflush.h>
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#include <asm/errata_list.h>
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#include <asm/patch.h>
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#include <asm/processor.h>
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#include <asm/sbi.h>
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#include <asm/vendorid_list.h>
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#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL
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#define ANDESTECH_AX45MP_MIMPID 0x500UL
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#define ANDESTECH_SBI_EXT_ANDES 0x0900031E
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#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1
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static long ax45mp_iocp_sw_workaround(void)
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{
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struct sbiret ret;
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/*
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* ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
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* cache is controllable only then CMO will be applied to the platform.
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*/
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ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
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0, 0, 0, 0, 0, 0);
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return ret.error ? 0 : ret.value;
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}
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static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid)
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{
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if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO))
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return false;
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if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)
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return false;
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if (!ax45mp_iocp_sw_workaround())
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return false;
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/* Set this just to make core cbo code happy */
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riscv_cbom_block_size = 1;
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riscv_noncoherent_supported();
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return true;
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}
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void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
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unsigned long archid, unsigned long impid,
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unsigned int stage)
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{
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errata_probe_iocp(stage, archid, impid);
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/* we have nothing to patch here ATM so just return back */
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}
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