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This patch implements consistent device DMA handling of memory management. DMA device operations are also here. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
195 lines
5.5 KiB
C
195 lines
5.5 KiB
C
/*
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* linux/arch/unicore32/include/asm/tlbflush.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_TLBFLUSH_H__
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#define __UNICORE_TLBFLUSH_H__
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long,
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struct vm_area_struct *);
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extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
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/*
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* TLB Management
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* ==============
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*
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* The arch/unicore/mm/tlb-*.S files implement these methods.
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*
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* The TLB specific code is expected to perform whatever tests it
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* needs to determine if it should invalidate the TLB for each
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* call. Start addresses are inclusive and end addresses are
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* exclusive; it is safe to round these addresses down.
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*
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* flush_tlb_all()
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*
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* Invalidate the entire TLB.
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*
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* flush_tlb_mm(mm)
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*
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* Invalidate all TLB entries in a particular address
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* space.
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* - mm - mm_struct describing address space
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*
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* flush_tlb_range(mm,start,end)
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*
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* Invalidate a range of TLB entries in the specified
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* address space.
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* - mm - mm_struct describing address space
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*
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* flush_tlb_page(vaddr,vma)
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*
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* Invalidate the specified page in the specified address range.
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* - vaddr - virtual address (may not be aligned)
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* - vma - vma_struct describing address range
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*
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* flush_kern_tlb_page(kaddr)
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*
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* Invalidate the TLB entry for the specified page. The address
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* will be in the kernels virtual memory space. Current uses
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* only require the D-TLB to be invalidated.
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* - kaddr - Kernel virtual memory address
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*/
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static inline void local_flush_tlb_all(void)
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{
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const int zero = 0;
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/* TLB invalidate all */
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asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (zero) : "cc");
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}
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static inline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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const int zero = 0;
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if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
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/* TLB invalidate all */
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asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (zero) : "cc");
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}
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put_cpu();
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}
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static inline void
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local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
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{
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
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#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE
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/* iTLB invalidate page */
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asm("movc p0.c6, %0, #5; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (uaddr & PAGE_MASK) : "cc");
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/* dTLB invalidate page */
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asm("movc p0.c6, %0, #3; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (uaddr & PAGE_MASK) : "cc");
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#else
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/* TLB invalidate all */
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asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (uaddr & PAGE_MASK) : "cc");
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#endif
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}
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}
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static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
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{
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#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE
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/* iTLB invalidate page */
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asm("movc p0.c6, %0, #5; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (kaddr & PAGE_MASK) : "cc");
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/* dTLB invalidate page */
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asm("movc p0.c6, %0, #3; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (kaddr & PAGE_MASK) : "cc");
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#else
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/* TLB invalidate all */
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asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (kaddr & PAGE_MASK) : "cc");
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#endif
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}
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/*
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* flush_pmd_entry
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*
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* Flush a PMD entry (word aligned, or double-word aligned) to
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* RAM if the TLB for the CPU we are running on requires this.
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* This is typically used when we are creating PMD entries.
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*
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* clean_pmd_entry
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*
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* Clean (but don't drain the write buffer) if the CPU requires
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* these operations. This is typically used when we are removing
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* PMD entries.
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*/
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static inline void flush_pmd_entry(pmd_t *pmd)
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{
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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
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/* flush dcache line, see dcacheline_flush in proc-macros.S */
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asm("mov r1, %0 << #20\n"
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"ldw r2, =_stext\n"
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"add r2, r2, r1 >> #20\n"
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"ldw r1, [r2+], #0x0000\n"
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"ldw r1, [r2+], #0x1000\n"
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"ldw r1, [r2+], #0x2000\n"
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"ldw r1, [r2+], #0x3000\n"
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: : "r" (pmd) : "r1", "r2");
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#else
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/* flush dcache all */
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asm("movc p0.c5, %0, #14; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (pmd) : "cc");
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#endif
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}
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static inline void clean_pmd_entry(pmd_t *pmd)
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{
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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
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/* clean dcache line */
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asm("movc p0.c5, %0, #11; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (__pa(pmd) & ~(L1_CACHE_BYTES - 1)) : "cc");
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#else
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/* clean dcache all */
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asm("movc p0.c5, %0, #10; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (pmd) : "cc");
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#endif
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}
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/*
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* Convert calls to our calling convention.
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*/
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#define local_flush_tlb_range(vma, start, end) \
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__cpu_flush_user_tlb_range(start, end, vma)
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#define local_flush_tlb_kernel_range(s, e) \
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__cpu_flush_kern_tlb_range(s, e)
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#define flush_tlb_all local_flush_tlb_all
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#define flush_tlb_mm local_flush_tlb_mm
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#define flush_tlb_page local_flush_tlb_page
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#define flush_tlb_kernel_page local_flush_tlb_kernel_page
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#define flush_tlb_range local_flush_tlb_range
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#define flush_tlb_kernel_range local_flush_tlb_kernel_range
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/*
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* if PG_dcache_clean is not set for the page, we need to ensure that any
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* cache entries for the kernels virtual memory range are written
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* back to the page.
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*/
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extern void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep);
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extern void do_bad_area(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs);
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#endif
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#endif
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