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Partial Reconfiguration (PR) is the most important function for FME. It allows reconfiguration for given Port/Accelerated Function Unit (AFU). It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges, and invokes fpga-region's interface (fpga_region_program_fpga) for PR operation once PR request received via ioctl. Below user space interface is exposed by this sub feature. Ioctl interface: * DFL_FPGA_FME_PORT_PR Do partial reconfiguration per information from userspace, including target port(AFU), buffer size and address info. It returns error code to userspace if failed. For detailed PR error information, user needs to read fpga-mgr's status sysfs interface. Signed-off-by: Tim Whisonant <tim.whisonant@intel.com> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com> Signed-off-by: Shiva Rao <shiva.rao@intel.com> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com> Signed-off-by: Kang Luwei <luwei.kang@intel.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
84 lines
2 KiB
C
84 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
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*
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* Copyright (C) 2017-2018 Intel Corporation, Inc.
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*
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* Authors:
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* Kang Luwei <luwei.kang@intel.com>
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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* Wu Hao <hao.wu@intel.com>
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* Joseph Grecco <joe.grecco@intel.com>
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* Enno Luebbers <enno.luebbers@intel.com>
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* Tim Whisonant <tim.whisonant@intel.com>
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* Ananda Ravuri <ananda.ravuri@intel.com>
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* Henry Mitchel <henry.mitchel@intel.com>
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*/
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#ifndef __DFL_FME_PR_H
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#define __DFL_FME_PR_H
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#include <linux/platform_device.h>
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/**
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* struct dfl_fme_region - FME fpga region data structure
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*
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* @region: platform device of the FPGA region.
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* @node: used to link fme_region to a list.
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* @port_id: indicate which port this region connected to.
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*/
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struct dfl_fme_region {
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struct platform_device *region;
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struct list_head node;
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int port_id;
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};
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/**
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* struct dfl_fme_region_pdata - platform data for FME region platform device.
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*
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* @mgr: platform device of the FPGA manager.
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* @br: platform device of the FPGA bridge.
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* @region_id: region id (same as port_id).
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*/
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struct dfl_fme_region_pdata {
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struct platform_device *mgr;
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struct platform_device *br;
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int region_id;
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};
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/**
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* struct dfl_fme_bridge - FME fpga bridge data structure
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*
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* @br: platform device of the FPGA bridge.
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* @node: used to link fme_bridge to a list.
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*/
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struct dfl_fme_bridge {
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struct platform_device *br;
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struct list_head node;
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};
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/**
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* struct dfl_fme_bridge_pdata - platform data for FME bridge platform device.
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*
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* @cdev: container device.
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* @port_id: port id.
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*/
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struct dfl_fme_br_pdata {
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struct dfl_fpga_cdev *cdev;
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int port_id;
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};
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/**
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* struct dfl_fme_mgr_pdata - platform data for FME manager platform device.
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*
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* @ioaddr: mapped io address for FME manager platform device.
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*/
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struct dfl_fme_mgr_pdata {
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void __iomem *ioaddr;
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};
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#define DFL_FPGA_FME_MGR "dfl-fme-mgr"
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#define DFL_FPGA_FME_BRIDGE "dfl-fme-bridge"
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#define DFL_FPGA_FME_REGION "dfl-fme-region"
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#endif /* __DFL_FME_PR_H */
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