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91d7f3f8f1
Fix up inconsistent usage of upper and lowercase letters in "Exynos" name. "EXYNOS" is not an abbreviation but a regular trademarked name. Therefore it should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
160 lines
3.9 KiB
C
160 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* exynos_ppmu.h - Exynos PPMU header file
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Author : Chanwoo Choi <cw00.choi@samsung.com>
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*/
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#ifndef __EXYNOS_PPMU_H__
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#define __EXYNOS_PPMU_H__
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enum ppmu_state {
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PPMU_DISABLE = 0,
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PPMU_ENABLE,
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};
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enum ppmu_counter {
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PPMU_PMNCNT0 = 0,
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PPMU_PMNCNT1,
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PPMU_PMNCNT2,
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PPMU_PMNCNT3,
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PPMU_PMNCNT_MAX,
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};
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/***
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* PPMUv1.1 Definitions
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*/
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enum ppmu_event_type {
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PPMU_RO_BUSY_CYCLE_CNT = 0x0,
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PPMU_WO_BUSY_CYCLE_CNT = 0x1,
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PPMU_RW_BUSY_CYCLE_CNT = 0x2,
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PPMU_RO_REQUEST_CNT = 0x3,
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PPMU_WO_REQUEST_CNT = 0x4,
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PPMU_RO_DATA_CNT = 0x5,
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PPMU_WO_DATA_CNT = 0x6,
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PPMU_RO_LATENCY = 0x12,
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PPMU_WO_LATENCY = 0x16,
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};
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enum ppmu_reg {
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/* PPC control register */
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PPMU_PMNC = 0x00,
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PPMU_CNTENS = 0x10,
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PPMU_CNTENC = 0x20,
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PPMU_INTENS = 0x30,
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PPMU_INTENC = 0x40,
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PPMU_FLAG = 0x50,
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/* Cycle Counter and Performance Event Counter Register */
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PPMU_CCNT = 0x100,
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PPMU_PMCNT0 = 0x110,
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PPMU_PMCNT1 = 0x120,
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PPMU_PMCNT2 = 0x130,
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PPMU_PMCNT3_HIGH = 0x140,
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PPMU_PMCNT3_LOW = 0x150,
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/* Bus Event Generator */
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PPMU_BEVT0SEL = 0x1000,
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PPMU_BEVT1SEL = 0x1100,
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PPMU_BEVT2SEL = 0x1200,
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PPMU_BEVT3SEL = 0x1300,
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PPMU_COUNTER_RESET = 0x1810,
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PPMU_READ_OVERFLOW_CNT = 0x1810,
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PPMU_READ_UNDERFLOW_CNT = 0x1814,
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PPMU_WRITE_OVERFLOW_CNT = 0x1850,
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PPMU_WRITE_UNDERFLOW_CNT = 0x1854,
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PPMU_READ_PENDING_CNT = 0x1880,
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PPMU_WRITE_PENDING_CNT = 0x1884
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};
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/* PMNC register */
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#define PPMU_PMNC_CC_RESET_SHIFT 2
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#define PPMU_PMNC_COUNTER_RESET_SHIFT 1
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#define PPMU_PMNC_ENABLE_SHIFT 0
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#define PPMU_PMNC_START_MODE_MASK BIT(16)
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#define PPMU_PMNC_CC_DIVIDER_MASK BIT(3)
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#define PPMU_PMNC_CC_RESET_MASK BIT(2)
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#define PPMU_PMNC_COUNTER_RESET_MASK BIT(1)
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#define PPMU_PMNC_ENABLE_MASK BIT(0)
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/* CNTENS/CNTENC/INTENS/INTENC/FLAG register */
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#define PPMU_CCNT_MASK BIT(31)
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#define PPMU_PMCNT3_MASK BIT(3)
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#define PPMU_PMCNT2_MASK BIT(2)
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#define PPMU_PMCNT1_MASK BIT(1)
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#define PPMU_PMCNT0_MASK BIT(0)
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/* PPMU_PMNCTx/PPMU_BETxSEL registers */
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#define PPMU_PMNCT(x) (PPMU_PMCNT0 + (0x10 * x))
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#define PPMU_BEVTxSEL(x) (PPMU_BEVT0SEL + (0x100 * x))
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/***
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* PPMU_V2.0 definitions
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*/
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enum ppmu_v2_mode {
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PPMU_V2_MODE_MANUAL = 0,
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PPMU_V2_MODE_AUTO = 1,
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PPMU_V2_MODE_CIG = 2, /* CIG (Conditional Interrupt Generation) */
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};
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enum ppmu_v2_event_type {
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PPMU_V2_RO_DATA_CNT = 0x4,
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PPMU_V2_WO_DATA_CNT = 0x5,
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PPMU_V2_EVT3_RW_DATA_CNT = 0x22, /* Only for Event3 */
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};
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enum ppmu_V2_reg {
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/* PPC control register */
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PPMU_V2_PMNC = 0x04,
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PPMU_V2_CNTENS = 0x08,
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PPMU_V2_CNTENC = 0x0c,
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PPMU_V2_INTENS = 0x10,
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PPMU_V2_INTENC = 0x14,
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PPMU_V2_FLAG = 0x18,
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/* Cycle Counter and Performance Event Counter Register */
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PPMU_V2_CCNT = 0x48,
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PPMU_V2_PMCNT0 = 0x34,
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PPMU_V2_PMCNT1 = 0x38,
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PPMU_V2_PMCNT2 = 0x3c,
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PPMU_V2_PMCNT3_LOW = 0x40,
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PPMU_V2_PMCNT3_HIGH = 0x44,
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/* Bus Event Generator */
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PPMU_V2_CIG_CFG0 = 0x1c,
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PPMU_V2_CIG_CFG1 = 0x20,
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PPMU_V2_CIG_CFG2 = 0x24,
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PPMU_V2_CIG_RESULT = 0x28,
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PPMU_V2_CNT_RESET = 0x2c,
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PPMU_V2_CNT_AUTO = 0x30,
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PPMU_V2_CH_EV0_TYPE = 0x200,
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PPMU_V2_CH_EV1_TYPE = 0x204,
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PPMU_V2_CH_EV2_TYPE = 0x208,
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PPMU_V2_CH_EV3_TYPE = 0x20c,
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PPMU_V2_SM_ID_V = 0x220,
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PPMU_V2_SM_ID_A = 0x224,
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PPMU_V2_SM_OTHERS_V = 0x228,
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PPMU_V2_SM_OTHERS_A = 0x22c,
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PPMU_V2_INTERRUPT_RESET = 0x260,
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};
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/* PMNC register */
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#define PPMU_V2_PMNC_START_MODE_SHIFT 20
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#define PPMU_V2_PMNC_START_MODE_MASK (0x3 << PPMU_V2_PMNC_START_MODE_SHIFT)
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#define PPMU_PMNC_CC_RESET_SHIFT 2
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#define PPMU_PMNC_COUNTER_RESET_SHIFT 1
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#define PPMU_PMNC_ENABLE_SHIFT 0
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#define PPMU_PMNC_START_MODE_MASK BIT(16)
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#define PPMU_PMNC_CC_DIVIDER_MASK BIT(3)
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#define PPMU_PMNC_CC_RESET_MASK BIT(2)
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#define PPMU_PMNC_COUNTER_RESET_MASK BIT(1)
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#define PPMU_PMNC_ENABLE_MASK BIT(0)
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#define PPMU_V2_PMNCT(x) (PPMU_V2_PMCNT0 + (0x4 * x))
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#define PPMU_V2_CH_EVx_TYPE(x) (PPMU_V2_CH_EV0_TYPE + (0x4 * x))
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#endif /* __EXYNOS_PPMU_H__ */
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