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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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7b6859fbdc
This pushes qed [and as result, all qed* drivers] into using 8.20.0.0 firmware. The changes are mostly contained in qed with minor changes to qedi due to some HSI changes. Content-wise, the firmware contains fixes to various issues exposed since the release of the previous firmware, including: - Corrects iSCSI fast retransmit when data digest is enabled. - Stop draining packets when receiving several consecutive PFCs. - Prevent possible assertion when consecutively opening/closing many connections. - Prevent possible assertion due to too long BDQ fetch time. In addition, the new firmware would allow us to later add iWARP support in qed and qedr. Changes from previous version ----------------------------- - V2: Fix warning in qed_debug.c Signed-off-by: Chad Dupuis <Chad.Dupuis@cavium.com> Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com> Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com> Signed-off-by: Manish Rangankar <Manish.Rangankar@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
451 lines
15 KiB
C
451 lines
15 KiB
C
/* QLogic qed NIC Driver
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* Copyright (c) 2015-2017 QLogic Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and /or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __ETH_COMMON__
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#define __ETH_COMMON__
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/********************/
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/* ETH FW CONSTANTS */
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/********************/
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#define ETH_HSI_VER_MAJOR 3
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#define ETH_HSI_VER_MINOR 10
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#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
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#define ETH_CACHE_LINE_SIZE 64
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#define ETH_RX_CQE_GAP 32
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#define ETH_MAX_RAMROD_PER_CON 8
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#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
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#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
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#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
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#define ETH_RX_NUM_NEXT_PAGE_BDS 2
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#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
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#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
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#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
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#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
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#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
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#define ETH_TX_MAX_LSO_HDR_NBD 4
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#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
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#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
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#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
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#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
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#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
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#define ETH_TX_MAX_LSO_HDR_BYTES 510
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#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
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#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
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#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
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#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
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#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
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#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
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#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
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(ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
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#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
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(ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
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/* Maximum number of buffers, used for RX packet placement */
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#define ETH_RX_MAX_BUFF_PER_PKT 5
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#define ETH_RX_BD_THRESHOLD 12
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/* num of MAC/VLAN filters */
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#define ETH_NUM_MAC_FILTERS 512
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#define ETH_NUM_VLAN_FILTERS 512
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/* approx. multicast constants */
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#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
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#define ETH_MULTICAST_MAC_BINS 256
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#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
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/* ethernet vport update constants */
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#define ETH_FILTER_RULES_COUNT 10
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#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
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#define ETH_RSS_KEY_SIZE_REGS 10
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#define ETH_RSS_ENGINE_NUM_K2 207
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#define ETH_RSS_ENGINE_NUM_BB 127
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/* TPA constants */
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#define ETH_TPA_MAX_AGGS_NUM 64
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#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
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#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
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#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
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/* Control frame check constants */
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#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
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struct eth_tx_1st_bd_flags {
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u8 bitfields;
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#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
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#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
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#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
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#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
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#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
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#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
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#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
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#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
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};
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/* The parsing information data fo rthe first tx bd of a given packet. */
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struct eth_tx_data_1st_bd {
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__le16 vlan;
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u8 nbds;
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struct eth_tx_1st_bd_flags bd_flags;
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__le16 bitfields;
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#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
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#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
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#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
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#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
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#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
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#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
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};
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/* The parsing information data for the second tx bd of a given packet. */
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struct eth_tx_data_2nd_bd {
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__le16 tunn_ip_size;
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__le16 bitfields1;
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#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
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#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
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#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
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#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
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#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
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#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
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#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
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#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
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#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
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#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
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#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
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#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
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#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
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#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
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#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
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#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
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#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
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#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
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#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
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#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
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__le16 bitfields2;
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#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
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#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
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#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
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#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
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};
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/* Firmware data for L2-EDPM packet. */
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struct eth_edpm_fw_data {
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struct eth_tx_data_1st_bd data_1st_bd;
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struct eth_tx_data_2nd_bd data_2nd_bd;
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__le32 reserved;
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};
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struct eth_fast_path_cqe_fw_debug {
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__le16 reserved2;
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};
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/* tunneling parsing flags */
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struct eth_tunnel_parsing_flags {
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u8 flags;
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#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
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#define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
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#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
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#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
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#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
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#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
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#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
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#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
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#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
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#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
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#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
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#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
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};
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/* PMD flow control bits */
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struct eth_pmd_flow_flags {
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u8 flags;
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#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
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#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
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#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
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#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
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#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
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#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
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};
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/* Regular ETH Rx FP CQE. */
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struct eth_fast_path_rx_reg_cqe {
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u8 type;
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u8 bitfields;
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#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
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#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
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#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
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#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
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#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
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#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
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__le16 pkt_len;
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struct parsing_and_err_flags pars_flags;
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__le16 vlan_tag;
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__le32 rss_hash;
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__le16 len_on_first_bd;
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u8 placement_offset;
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struct eth_tunnel_parsing_flags tunnel_pars_flags;
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u8 bd_num;
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u8 reserved[9];
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struct eth_fast_path_cqe_fw_debug fw_debug;
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u8 reserved1[3];
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struct eth_pmd_flow_flags pmd_flags;
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};
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/* TPA-continue ETH Rx FP CQE. */
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struct eth_fast_path_rx_tpa_cont_cqe {
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u8 type;
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u8 tpa_agg_index;
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__le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
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u8 reserved;
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u8 reserved1;
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__le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
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u8 reserved3[3];
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struct eth_pmd_flow_flags pmd_flags;
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};
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/* TPA-end ETH Rx FP CQE. */
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struct eth_fast_path_rx_tpa_end_cqe {
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u8 type;
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u8 tpa_agg_index;
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__le16 total_packet_len;
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u8 num_of_bds;
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u8 end_reason;
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__le16 num_of_coalesced_segs;
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__le32 ts_delta;
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__le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
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__le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
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__le16 reserved1;
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u8 reserved2;
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struct eth_pmd_flow_flags pmd_flags;
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};
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/* TPA-start ETH Rx FP CQE. */
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struct eth_fast_path_rx_tpa_start_cqe {
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u8 type;
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u8 bitfields;
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#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
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#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
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#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
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#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
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#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
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#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
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__le16 seg_len;
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struct parsing_and_err_flags pars_flags;
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__le16 vlan_tag;
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__le32 rss_hash;
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__le16 len_on_first_bd;
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u8 placement_offset;
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struct eth_tunnel_parsing_flags tunnel_pars_flags;
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u8 tpa_agg_index;
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u8 header_len;
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__le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
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struct eth_fast_path_cqe_fw_debug fw_debug;
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u8 reserved;
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struct eth_pmd_flow_flags pmd_flags;
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};
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/* The L4 pseudo checksum mode for Ethernet */
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enum eth_l4_pseudo_checksum_mode {
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ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
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ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
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MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
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};
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struct eth_rx_bd {
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struct regpair addr;
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};
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/* regular ETH Rx SP CQE */
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struct eth_slow_path_rx_cqe {
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u8 type;
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u8 ramrod_cmd_id;
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u8 error_flag;
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u8 reserved[25];
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__le16 echo;
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u8 reserved1;
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struct eth_pmd_flow_flags pmd_flags;
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};
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/* union for all ETH Rx CQE types */
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union eth_rx_cqe {
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struct eth_fast_path_rx_reg_cqe fast_path_regular;
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struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
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struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
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struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
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struct eth_slow_path_rx_cqe slow_path;
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};
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/* ETH Rx CQE type */
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enum eth_rx_cqe_type {
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ETH_RX_CQE_TYPE_UNUSED,
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ETH_RX_CQE_TYPE_REGULAR,
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ETH_RX_CQE_TYPE_SLOW_PATH,
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ETH_RX_CQE_TYPE_TPA_START,
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ETH_RX_CQE_TYPE_TPA_CONT,
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ETH_RX_CQE_TYPE_TPA_END,
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MAX_ETH_RX_CQE_TYPE
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};
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struct eth_rx_pmd_cqe {
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union eth_rx_cqe cqe;
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u8 reserved[ETH_RX_CQE_GAP];
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};
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enum eth_rx_tunn_type {
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ETH_RX_NO_TUNN,
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ETH_RX_TUNN_GENEVE,
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ETH_RX_TUNN_GRE,
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ETH_RX_TUNN_VXLAN,
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MAX_ETH_RX_TUNN_TYPE
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};
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/* Aggregation end reason. */
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enum eth_tpa_end_reason {
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ETH_AGG_END_UNUSED,
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ETH_AGG_END_SP_UPDATE,
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ETH_AGG_END_MAX_LEN,
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ETH_AGG_END_LAST_SEG,
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ETH_AGG_END_TIMEOUT,
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ETH_AGG_END_NOT_CONSISTENT,
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ETH_AGG_END_OUT_OF_ORDER,
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ETH_AGG_END_NON_TPA_SEG,
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MAX_ETH_TPA_END_REASON
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};
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/* The first tx bd of a given packet */
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struct eth_tx_1st_bd {
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struct regpair addr;
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__le16 nbytes;
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struct eth_tx_data_1st_bd data;
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};
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/* The second tx bd of a given packet */
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struct eth_tx_2nd_bd {
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struct regpair addr;
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__le16 nbytes;
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struct eth_tx_data_2nd_bd data;
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};
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/* The parsing information data for the third tx bd of a given packet. */
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struct eth_tx_data_3rd_bd {
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__le16 lso_mss;
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__le16 bitfields;
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#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
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#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
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#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
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#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
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#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
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#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
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#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
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#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
|
|
u8 tunn_l4_hdr_start_offset_w;
|
|
u8 tunn_hdr_size_w;
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|
};
|
|
|
|
/* The third tx bd of a given packet */
|
|
struct eth_tx_3rd_bd {
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|
struct regpair addr;
|
|
__le16 nbytes;
|
|
struct eth_tx_data_3rd_bd data;
|
|
};
|
|
|
|
/* Complementary information for the regular tx bd of a given packet. */
|
|
struct eth_tx_data_bd {
|
|
__le16 reserved0;
|
|
__le16 bitfields;
|
|
#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
|
|
#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
|
|
#define ETH_TX_DATA_BD_START_BD_MASK 0x1
|
|
#define ETH_TX_DATA_BD_START_BD_SHIFT 8
|
|
#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
|
|
#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
|
|
__le16 reserved3;
|
|
};
|
|
|
|
/* The common non-special TX BD ring element */
|
|
struct eth_tx_bd {
|
|
struct regpair addr;
|
|
__le16 nbytes;
|
|
struct eth_tx_data_bd data;
|
|
};
|
|
|
|
union eth_tx_bd_types {
|
|
struct eth_tx_1st_bd first_bd;
|
|
struct eth_tx_2nd_bd second_bd;
|
|
struct eth_tx_3rd_bd third_bd;
|
|
struct eth_tx_bd reg_bd;
|
|
};
|
|
|
|
/* Mstorm Queue Zone */
|
|
enum eth_tx_tunn_type {
|
|
ETH_TX_TUNN_GENEVE,
|
|
ETH_TX_TUNN_TTAG,
|
|
ETH_TX_TUNN_GRE,
|
|
ETH_TX_TUNN_VXLAN,
|
|
MAX_ETH_TX_TUNN_TYPE
|
|
};
|
|
|
|
/* Ystorm Queue Zone */
|
|
struct xstorm_eth_queue_zone {
|
|
struct coalescing_timeset int_coalescing_timeset;
|
|
u8 reserved[7];
|
|
};
|
|
|
|
/* ETH doorbell data */
|
|
struct eth_db_data {
|
|
u8 params;
|
|
#define ETH_DB_DATA_DEST_MASK 0x3
|
|
#define ETH_DB_DATA_DEST_SHIFT 0
|
|
#define ETH_DB_DATA_AGG_CMD_MASK 0x3
|
|
#define ETH_DB_DATA_AGG_CMD_SHIFT 2
|
|
#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
|
|
#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
|
|
#define ETH_DB_DATA_RESERVED_MASK 0x1
|
|
#define ETH_DB_DATA_RESERVED_SHIFT 5
|
|
#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
|
|
#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
|
|
u8 agg_flags;
|
|
__le16 bd_prod;
|
|
};
|
|
|
|
#endif /* __ETH_COMMON__ */
|