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10d443431d
Some ARC CPU's do not support unaligned loads/stores. Currently, generic
implementation of reads{b/w/l}()/writes{b/w/l}() is being used with ARC.
This can lead to misfunction of some drivers as generic functions do a
plain dereference of a pointer that can be unaligned.
Let's use {get/put}_unaligned() helpers instead of plain dereference of
pointer in order to fix. The helpers allow to get and store data from an
unaligned address whilst preserving the CPU internal alignment.
According to [1], the use of these helpers are costly in terms of
performance so we added an initial check for a buffer already aligned so
that the usage of the helpers can be avoided, when possible.
[1] Documentation/unaligned-memory-access.txt
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David Laight <David.Laight@ACULAB.COM>
Tested-by: Vitor Soares <soares@synopsys.com>
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
242 lines
6.4 KiB
C
242 lines
6.4 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_IO_H
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#define _ASM_ARC_IO_H
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <asm/page.h>
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#include <asm/unaligned.h>
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#ifdef CONFIG_ISA_ARCV2
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#include <asm/barrier.h>
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#else
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#define __iormb() do { } while (0)
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#define __iowmb() do { } while (0)
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#endif
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extern void __iomem *ioremap(phys_addr_t paddr, unsigned long size);
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extern void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size,
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unsigned long flags);
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static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
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{
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return (void __iomem *)port;
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}
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static inline void ioport_unmap(void __iomem *addr)
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{
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}
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extern void iounmap(const void __iomem *addr);
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#define ioremap_nocache(phy, sz) ioremap(phy, sz)
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#define ioremap_wc(phy, sz) ioremap(phy, sz)
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#define ioremap_wt(phy, sz) ioremap(phy, sz)
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/*
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* io{read,write}{16,32}be() macros
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*/
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#define ioread16be(p) ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
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#define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
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#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })
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#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })
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/* Change struct page to physical address */
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#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 b;
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__asm__ __volatile__(
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" ldb%U1 %0, %1 \n"
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: "=r" (b)
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: "m" (*(volatile u8 __force *)addr)
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: "memory");
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return b;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 s;
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__asm__ __volatile__(
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" ldw%U1 %0, %1 \n"
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: "=r" (s)
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: "m" (*(volatile u16 __force *)addr)
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: "memory");
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return s;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 w;
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__asm__ __volatile__(
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" ld%U1 %0, %1 \n"
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: "=r" (w)
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: "m" (*(volatile u32 __force *)addr)
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: "memory");
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return w;
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}
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/*
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* {read,write}s{b,w,l}() repeatedly access the same IO address in
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* native endianness in 8-, 16-, 32-bit chunks {into,from} memory,
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* @count times
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*/
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#define __raw_readsx(t,f) \
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static inline void __raw_reads##f(const volatile void __iomem *addr, \
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void *ptr, unsigned int count) \
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{ \
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bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0; \
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u##t *buf = ptr; \
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\
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if (!count) \
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return; \
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\
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/* Some ARC CPU's don't support unaligned accesses */ \
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if (is_aligned) { \
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do { \
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u##t x = __raw_read##f(addr); \
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*buf++ = x; \
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} while (--count); \
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} else { \
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do { \
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u##t x = __raw_read##f(addr); \
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put_unaligned(x, buf++); \
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} while (--count); \
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} \
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}
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#define __raw_readsb __raw_readsb
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__raw_readsx(8, b)
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#define __raw_readsw __raw_readsw
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__raw_readsx(16, w)
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#define __raw_readsl __raw_readsl
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__raw_readsx(32, l)
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
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{
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__asm__ __volatile__(
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" stb%U1 %0, %1 \n"
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:
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: "r" (b), "m" (*(volatile u8 __force *)addr)
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: "memory");
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 s, volatile void __iomem *addr)
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{
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__asm__ __volatile__(
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" stw%U1 %0, %1 \n"
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:
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: "r" (s), "m" (*(volatile u16 __force *)addr)
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: "memory");
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 w, volatile void __iomem *addr)
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{
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__asm__ __volatile__(
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" st%U1 %0, %1 \n"
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:
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: "r" (w), "m" (*(volatile u32 __force *)addr)
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: "memory");
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}
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#define __raw_writesx(t,f) \
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static inline void __raw_writes##f(volatile void __iomem *addr, \
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const void *ptr, unsigned int count) \
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{ \
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bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0; \
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const u##t *buf = ptr; \
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\
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if (!count) \
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return; \
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\
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/* Some ARC CPU's don't support unaligned accesses */ \
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if (is_aligned) { \
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do { \
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__raw_write##f(*buf++, addr); \
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} while (--count); \
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} else { \
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do { \
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__raw_write##f(get_unaligned(buf++), addr); \
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} while (--count); \
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} \
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}
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#define __raw_writesb __raw_writesb
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__raw_writesx(8, b)
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#define __raw_writesw __raw_writesw
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__raw_writesx(16, w)
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#define __raw_writesl __raw_writesl
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__raw_writesx(32, l)
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/*
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* MMIO can also get buffered/optimized in micro-arch, so barriers needed
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* Based on ARM model for the typical use case
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*
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* <ST [DMA buffer]>
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* <writel MMIO "go" reg>
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* or:
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* <readl MMIO "status" reg>
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* <LD [DMA buffer]>
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*
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* http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
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*/
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define readsb(p,d,l) ({ __raw_readsb(p,d,l); __iormb(); })
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#define readsw(p,d,l) ({ __raw_readsw(p,d,l); __iormb(); })
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#define readsl(p,d,l) ({ __raw_readsl(p,d,l); __iormb(); })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
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#define writesb(p,d,l) ({ __iowmb(); __raw_writesb(p,d,l); })
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#define writesw(p,d,l) ({ __iowmb(); __raw_writesw(p,d,l); })
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#define writesl(p,d,l) ({ __iowmb(); __raw_writesl(p,d,l); })
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/*
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* Relaxed API for drivers which can handle barrier ordering themselves
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*
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* Also these are defined to perform little endian accesses.
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* To provide the typical device register semantics of fixed endian,
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* swap the byte order for Big Endian
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*
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* http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
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*/
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#define readb_relaxed(c) __raw_readb(c)
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __r; })
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#define writeb_relaxed(v,c) __raw_writeb(v,c)
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#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
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#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
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#include <asm-generic/io.h>
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#endif /* _ASM_ARC_IO_H */
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