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123ee7550e
Add the MDSS_CORE reset which can be asserted to reset the state of the entire MDSS. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316-topic-qcm_dispcc_reset-v1-1-dd3708853014@linaro.org
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H
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/* DISP_CC clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define DISP_CC_MDSS_ESC0_CLK 7
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#define DISP_CC_MDSS_ESC0_CLK_SRC 8
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#define DISP_CC_MDSS_MDP_CLK 9
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#define DISP_CC_MDSS_MDP_CLK_SRC 10
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#define DISP_CC_MDSS_MDP_LUT_CLK 11
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12
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#define DISP_CC_MDSS_PCLK0_CLK 13
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 14
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#define DISP_CC_MDSS_VSYNC_CLK 15
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 16
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#define DISP_CC_SLEEP_CLK 17
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#define DISP_CC_SLEEP_CLK_SRC 18
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#define DISP_CC_XO_CLK 19
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#define DISP_CC_XO_CLK_SRC 20
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/* GDSCs */
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#define MDSS_GDSC 0
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/* Resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#endif
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