Max Filippov 839769c354 xtensa: fix a7 clobbering in coprocessor context load/store ... Fast coprocessor exception handler saves a3..a6, but coprocessor context load/store code uses a4..a7 as temporaries, potentially clobbering a7. 'Potentially' because coprocessor state load/store macros may not use all four temporary registers (and neither FPU nor HiFi macros do). Use a3..a6 as intended. Cc: stable@vger.kernel.org Fixes: c658eac628 ("[XTENSA] Add support for configurable registers and coprocessors") Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2022-04-15 18:44:02 -07:00
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kernel	xtensa: fix a7 clobbering in coprocessor context load/store	2022-04-15 18:44:02 -07:00
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platforms	arch: xtensa: platforms: Fix deadlock in rs_close()	2022-04-13 03:36:34 -07:00
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