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c6e58ebb37
Patch from Ben Dooks The IRQ_EINT0 through IRQ_EINT3 handling has changed on the S3C2412 from the previous SoCs in the range, and thus we need to add code to handle this. The changes come about due to these IRQs being displayed in two different registers, and needing to be acked and masked in both. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
130 lines
3.3 KiB
C
130 lines
3.3 KiB
C
/* linux/arch/arm/mach-s3c2412/s3c2412-irq.c
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/ptrace.h>
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/regs-irq.h>
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#include <asm/arch/regs-gpio.h>
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#include "cpu.h"
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#include "irq.h"
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/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
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* having them turn up in both the INT* and the EINT* registers. Whilst
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* both show the status, they both now need to be acked when the IRQs
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* go off.
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*/
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static void
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s3c2412_irq_mask(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask | bitval, S3C2410_INTMSK);
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask | bitval, S3C2412_EINTMASK);
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}
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static inline void
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s3c2412_irq_ack(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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__raw_writel(bitval, S3C2412_EINTPEND);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static inline void
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s3c2412_irq_maskack(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask|bitval, S3C2410_INTMSK);
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask | bitval, S3C2412_EINTMASK);
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__raw_writel(bitval, S3C2412_EINTPEND);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static void
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s3c2412_irq_unmask(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask & ~bitval, S3C2412_EINTMASK);
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask & ~bitval, S3C2410_INTMSK);
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}
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static struct irqchip s3c2412_irq_eint0t4 = {
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.ack = s3c2412_irq_ack,
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.mask = s3c2412_irq_mask,
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.unmask = s3c2412_irq_unmask,
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.set_wake = s3c_irq_wake,
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.set_type = s3c_irqext_type,
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};
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static int s3c2412_irq_add(struct sys_device *sysdev)
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{
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unsigned int irqno;
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for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
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set_irq_chip(irqno, &s3c2412_irq_eint0t4);
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set_irq_handler(irqno, do_edge_IRQ);
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set_irq_flags(irqno, IRQF_VALID);
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}
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return 0;
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}
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static struct sysdev_driver s3c2412_irq_driver = {
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.add = s3c2412_irq_add,
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};
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static int s3c2412_irq_init(void)
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{
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return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver);
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}
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arch_initcall(s3c2412_irq_init);
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