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3d5e80125a
Accumulator is present in configs with FPU and/or DSP MPY (mpy > 6) Instead of doing this in pt_regs (and thus every kernel entry/exit), this could have been done in context switch (and for user task only) as currently kernel doesn't clobber these registers for its own accord. However we will soon start using 64-bit multiply instructions for kernel which can clobber these. Also gcc folks also plan to start using these as GPRs, hence better to always save/restore them Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
202 lines
4.1 KiB
C
202 lines
4.1 KiB
C
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#ifndef __ASM_ARC_ENTRY_ARCV2_H
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#define __ASM_ARC_ENTRY_ARCV2_H
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#include <asm/asm-offsets.h>
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#include <asm/irqflags-arcv2.h>
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#include <asm/thread_info.h> /* For THREAD_SIZE */
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/*------------------------------------------------------------------------*/
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.macro INTERRUPT_PROLOGUE called_from
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; Before jumping to Interrupt Vector, hardware micro-ops did following:
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; 1. SP auto-switched to kernel mode stack
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; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1, K:0)
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; 3. Auto saved: r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI, PC, STAT32
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;
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; Now manually save: r12, sp, fp, gp, r25
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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PUSH r59
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PUSH r58
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#endif
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PUSH r30
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PUSH r12
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; Saving pt_regs->sp correctly requires some extra work due to the way
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; Auto stack switch works
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; - U mode: retrieve it from AUX_USER_SP
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; - K mode: add the offset from current SP where H/w starts auto push
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;
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; Utilize the fact that Z bit is set if Intr taken in U mode
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mov.nz r9, sp
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add.nz r9, r9, SZ_PT_REGS - PT_sp - 4
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bnz 1f
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lr r9, [AUX_USER_SP]
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1:
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PUSH r9 ; SP
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PUSH fp
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PUSH gp
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#ifdef CONFIG_ARC_CURR_IN_REG
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PUSH r25 ; user_r25
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GET_CURR_TASK_ON_CPU r25
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#else
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sub sp, sp, 4
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#endif
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.ifnc \called_from, exception
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sub sp, sp, 12 ; BTA/ECR/orig_r0 placeholder per pt_regs
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.endif
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.endm
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/*------------------------------------------------------------------------*/
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.macro INTERRUPT_EPILOGUE called_from
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.ifnc \called_from, exception
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add sp, sp, 12 ; skip BTA/ECR/orig_r0 placeholderss
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.endif
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#ifdef CONFIG_ARC_CURR_IN_REG
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POP r25
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#else
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add sp, sp, 4
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#endif
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POP gp
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POP fp
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; Don't touch AUX_USER_SP if returning to K mode (Z bit set)
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; (Z bit set on K mode is inverse of INTERRUPT_PROLOGUE)
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add.z sp, sp, 4
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bz 1f
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POPAX AUX_USER_SP
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1:
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POP r12
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POP r30
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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POP r58
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POP r59
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#endif
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.endm
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/*------------------------------------------------------------------------*/
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.macro EXCEPTION_PROLOGUE
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; Before jumping to Exception Vector, hardware micro-ops did following:
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; 1. SP auto-switched to kernel mode stack
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; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1,K:0)
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;
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; Now manually save the complete reg file
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PUSH r9 ; freeup a register: slot of erstatus
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PUSHAX eret
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sub sp, sp, 12 ; skip JLI, LDI, EI
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PUSH lp_count
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PUSHAX lp_start
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PUSHAX lp_end
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PUSH blink
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PUSH r11
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PUSH r10
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ld.as r9, [sp, 10] ; load stashed r9 (status32 stack slot)
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lr r10, [erstatus]
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st.as r10, [sp, 10] ; save status32 at it's right stack slot
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PUSH r9
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PUSH r8
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PUSH r7
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PUSH r6
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PUSH r5
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PUSH r4
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PUSH r3
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PUSH r2
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PUSH r1
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PUSH r0
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; -- for interrupts, regs above are auto-saved by h/w in that order --
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; Now do what ISR prologue does (manually save r12, sp, fp, gp, r25)
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;
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; Set Z flag if this was from U mode (expected by INTERRUPT_PROLOGUE)
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; Although H/w exception micro-ops do set Z flag for U mode (just like
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; for interrupts), it could get clobbered in case we soft land here from
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; a TLB Miss exception handler (tlbex.S)
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and r10, r10, STATUS_U_MASK
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xor.f 0, r10, STATUS_U_MASK
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INTERRUPT_PROLOGUE exception
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PUSHAX erbta
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PUSHAX ecr ; r9 contains ECR, expected by EV_Trap
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PUSH r0 ; orig_r0
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.endm
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/*------------------------------------------------------------------------*/
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.macro EXCEPTION_EPILOGUE
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; Assumes r0 has PT_status32
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btst r0, STATUS_U_BIT ; Z flag set if K, used in INTERRUPT_EPILOGUE
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add sp, sp, 8 ; orig_r0/ECR don't need restoring
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POPAX erbta
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INTERRUPT_EPILOGUE exception
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POP r0
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POP r1
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POP r2
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POP r3
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POP r4
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POP r5
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POP r6
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POP r7
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POP r8
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POP r9
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POP r10
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POP r11
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POP blink
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POPAX lp_end
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POPAX lp_start
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POP r9
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mov lp_count, r9
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add sp, sp, 12 ; skip JLI, LDI, EI
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POPAX eret
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POPAX erstatus
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ld.as r9, [sp, -12] ; reload r9 which got clobbered
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.endm
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.macro FAKE_RET_FROM_EXCPN
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lr r9, [status32]
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bic r9, r9, (STATUS_U_MASK|STATUS_DE_MASK|STATUS_AE_MASK)
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or r9, r9, (STATUS_L_MASK|STATUS_IE_MASK)
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kflag r9
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.endm
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/* Get thread_info of "current" tsk */
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.macro GET_CURR_THR_INFO_FROM_SP reg
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bmskn \reg, sp, THREAD_SHIFT - 1
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.endm
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/* Get CPU-ID of this core */
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.macro GET_CPU_ID reg
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lr \reg, [identity]
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xbfu \reg, \reg, 0xE8 /* 00111 01000 */
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/* M = 8-1 N = 8 */
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.endm
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#endif
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