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![Yuriy Kolerov](/assets/img/avatar_default.png)
After reset all interrupts in the core interrupt controller has the highest priority P0. If the platform supports Fast IRQs and has more than 1 banks of registers then CPU automatically switch banks of registers when P0 interrupt comes. The problem is that the kernel expects that by default switching of banks is not used by all interrupts. It is necessary to set a default nonzero priority for all available interrupts to avoid undefined behaviour. Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
183 lines
4.9 KiB
C
183 lines
4.9 KiB
C
/*
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* Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <asm/irq.h>
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#define NR_EXCEPTIONS 16
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struct bcr_irq_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
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#else
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unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
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#endif
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};
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/*
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* Early Hardware specific Interrupt setup
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* -Called very early (start_kernel -> setup_arch -> setup_processor)
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* -Platform Independent (must for any ARC Core)
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* -Needed for each CPU (hence not foldable into init_IRQ)
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*/
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void arc_init_IRQ(void)
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{
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unsigned int tmp, irq_prio, i;
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struct bcr_irq_arcv2 irq_bcr;
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struct aux_irq_ctrl {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int res3:18, save_idx_regs:1, res2:1,
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save_u_to_u:1, save_lp_regs:1, save_blink:1,
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res:4, save_nr_gpr_pairs:5;
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#else
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unsigned int save_nr_gpr_pairs:5, res:4,
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save_blink:1, save_lp_regs:1, save_u_to_u:1,
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res2:1, save_idx_regs:1, res3:18;
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#endif
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} ictrl;
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*(unsigned int *)&ictrl = 0;
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ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */
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ictrl.save_blink = 1;
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ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */
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ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */
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ictrl.save_idx_regs = 1; /* JLI, LDI, EI */
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WRITE_AUX(AUX_IRQ_CTRL, ictrl);
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/*
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* ARCv2 core intc provides multiple interrupt priorities (upto 16).
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* Typical builds though have only two levels (0-high, 1-low)
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* Linux by default uses lower prio 1 for most irqs, reserving 0 for
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* NMI style interrupts in future (say perf)
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*/
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READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
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irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */
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pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
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irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
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irq_bcr.firq ? " FIRQ (not used)":"");
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/*
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* Set a default priority for all available interrupts to prevent
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* switching of register banks if Fast IRQ and multiple register banks
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* are supported by CPU.
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*/
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for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
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write_aux_reg(AUX_IRQ_SELECT, i);
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write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
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}
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/* setup status32, don't enable intr yet as kernel doesn't want */
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tmp = read_aux_reg(ARC_REG_STATUS32);
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tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
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tmp &= ~STATUS_IE_MASK;
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asm volatile("kflag %0 \n"::"r"(tmp));
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}
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static void arcv2_irq_mask(struct irq_data *data)
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{
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write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
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write_aux_reg(AUX_IRQ_ENABLE, 0);
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}
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static void arcv2_irq_unmask(struct irq_data *data)
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{
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write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
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write_aux_reg(AUX_IRQ_ENABLE, 1);
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}
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void arcv2_irq_enable(struct irq_data *data)
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{
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/* set default priority */
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write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
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write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
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/*
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* hw auto enables (linux unmask) all by default
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* So no need to do IRQ_ENABLE here
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* XXX: However OSCI LAN need it
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*/
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write_aux_reg(AUX_IRQ_ENABLE, 1);
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}
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static struct irq_chip arcv2_irq_chip = {
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.name = "ARCv2 core Intc",
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.irq_mask = arcv2_irq_mask,
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.irq_unmask = arcv2_irq_unmask,
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.irq_enable = arcv2_irq_enable
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};
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static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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/*
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* core intc IRQs [16, 23]:
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* Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
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*/
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if (hw < FIRST_EXT_IRQ) {
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/*
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* A subsequent request_percpu_irq() fails if percpu_devid is
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* not set. That in turns sets NOAUTOEN, meaning each core needs
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* to call enable_percpu_irq()
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*/
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irq_set_percpu_devid(irq);
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irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq);
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} else {
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irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq);
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}
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return 0;
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}
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static const struct irq_domain_ops arcv2_irq_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = arcv2_irq_map,
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};
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static int __init
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init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
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{
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struct irq_domain *root_domain;
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struct bcr_irq_arcv2 irq_bcr;
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unsigned int nr_cpu_irqs;
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READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
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nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS;
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if (parent)
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panic("DeviceTree incore intc not a root irq controller\n");
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root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
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if (!root_domain)
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panic("root irq domain not avail\n");
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/*
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* Needed for primary domain lookup to succeed
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* This is a primary irqchip, and can never have a parent
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*/
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irq_set_default_host(root_domain);
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#ifdef CONFIG_SMP
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irq_create_mapping(root_domain, IPI_IRQ);
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#endif
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irq_create_mapping(root_domain, SOFTIRQ_IRQ);
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return 0;
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}
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IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ);
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